Nuvoton Technology Corporation Japan

Tsubasa Inoue

Ryosuke Okawa

Kazuma Yoshida

Takeshi Imamura

Toshikazu Imai

Akira Kimura

Hironao Nakamura

Yusuke Ito

Masahiro Mitsuda

Eiji Yasuda

Takahiro Maeda

Eiichi Hirai

A semiconductor device has a shape of a rectangular in which the side length in a first direction is greater than or equal to the side length in a second direction in a plan view, and includes 2n+1 obround first source pads of a first vertical MOS transistor that are arranged in stripes at positions within a first area and extend in the second direction and 2n+1 obround second source pads of a second vertical MOS transistor that are arranged in stripes at positions within a second area and extend in the second direction.

Semiconductor device

A semiconductor device includes: a transistor provided in a first region of a semiconductor layer in a plan view; a transistor provided in a second region adjacent to the first region of the semiconductor layer in the plan view; and a drain pad provided in a third region not overlapping the first region and the second region in the plan view. In the plan view, the first region and the second region are one region and an other region that divide an area of the semiconductor layer excluding the third region in half. In the plan view, the transistors are arranged in a first direction. The center of the third region is located on a straight center line that divides the semiconductor layer in half in the first direction and is orthogonal to the first direction. In the plan view, the drain pad is contained in the third region.

A semiconductor device includes a first transistor disposed in a first region of a semiconductor layer and a second transistor disposed in a second region of the semiconductor layer, and includes, on the surface of the semiconductor layer, first source pads, a first gate pad, second source pads, and a second gate pad. In the plan view of the semiconductor layer, the first and second transistors are aligned in a first direction; the first gate pad is disposed such that none of the first source pads is disposed between the first gate pad and a side parallel to the first direction and located closest to the first gate pad; and the second gate pad is disposed such that none of the second source pads is disposed between the second gate pad and a side parallel to the first direction and located closest to the second gate pad.

Provided is a first vertical field effect transistor in which first source regions and first connection portions via which a first body region is connected to a first source electrode are disposed alternately and cyclically in a first direction in which first trenches extend. In a second direction orthogonal to the first direction, Lxm&#x2264;Lxr&#x2264;0.20 &#x3bc;m holds true where Lxm denotes a distance between adjacent first trenches and Lxr denotes the inner width of a first trench. The lengths of the first connection portions are in a convergence region in which the on-resistance of the vertical field effect transistor at the time when a voltage having a specification value is applied to first gate conductors to supply current having a specification value does not decrease noticeably even when the lengths of the first connection portions are made much shorter.

Provided is a semiconductor device which is a facedown mounting, chip-size-package-type semiconductor device and includes: a transistor element including a first electrode, a second electrode, and a control electrode which controls a conduction state between the first electrode and the second electrode; a plurality of first resistor elements each including a first electrode and a second electrode, the first electrodes of the first resistor elements being electrically connected to the second electrode of the transistor element; one or more external resistance terminals to which the second electrodes of the plurality of first resistor elements are physically connected; a first external terminal electrically connected to the first electrode of the transistor element; and an external control terminal electrically connected to the control electrode. The one or more external resistance terminals, the first external terminal, and the external control terminal are external connection terminals provided on a surface of the semiconductor device.

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Osaka, Japan

Tsubasa Inoue