Intel Corporation

Tsuan-Chung Chang

Tahir Ghani

Leonard P Guler

Biswajeet Guha

Charles Henry Wallace

Hossam A Abdallah

Robert Joachim

Shengsi Liu

Peter P Sun

Virupaxi Goornavar

Dario Farias

Chia-Ho Tsai

Chetana Singh

Desalegne Teweldebrhan

Techniques are provided herein to form an integrated circuit having gate cut structures or plug structures between source or drain regions, with an angled cut made to the top portion of the structures. In an example, a semiconductor device includes a semiconductor region extending between source and drain regions, and a gate structure extending over the semiconductor region. A gate cut structure is present adjacent to the semiconductor device and interrupts the gate structure. The gate cut structure has a first width along a first plane that extends through the semiconductor region and a second width along a second plane parallel to the first plane and above the semiconductor region, where the first width is greater than the second width. Similar angled plug structures may be provided adjacent to the source and drain regions to increase the landing area made to the metal contacts on the source and drain regions.

Angled gate or diffusion plugs

Fin cuts in neighboring gate and source or drain regions for advanced integrated circuit structure fabrication is described. For example, an integrated circuit structure includes a horizontal stack of semiconductor nanowire portions. A dielectric gate spacer is vertically over the horizontal stack of semiconductor nanowire portions. A gate isolation structure is laterally adjacent to a first side of the horizontal stack of semiconductor nanowire portions. A source or drain isolation structure is laterally adjacent to a second side of the horizontal stack of semiconductor nanowire portions.

Fin cut in neighboring gate and source or drain regions for advanced integrated circuit structure fabrication

Techniques for improved extreme ultraviolet (EUV) patterning using assist features, related transistor structures, integrated circuits, and systems, are disclosed. A number of semiconductor fins and assist features are patterned into a semiconductor substrate using EUV. The assist features increase coverage of absorber material in the EUV mask, thereby reducing bright field defects in the EUV patterning. The semiconductor fins and assist features are buried in fill material and a mask is patterned that exposes the assist features and covers the semiconductor fins. The exposed assist features are partially removed and the protected active fins are ultimately used in transistor devices.

Extreme ultraviolet lithography patterning with assist features

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Portland, OR, United States of America

Tsuan-Chung Chang