Progressant Technologies, Inc.

Synopsys, Inc.

University of California

Other

Progressent Technologies, Inc.

Tsu-Jae King

David K Y Liu

Victor Moroz

Roger T Howe

Chenming Hu

Hideki Takeuchi

Igor Polishchuk

Emmanuel Philippe Quevy

Hei Kam

Pushkar Ranade

Ya-Chin King

Chen Ming Hu

Andrea Franke

Leland Chang

Wen-Chin Lee

Vivek Subramanian

Ka-Ngo Leung

Jeffrey Bokor

Qing Ji

Keith Standiford

David Ky Liu

Yang-Kyu Choi

Kyoungsub Shin

Min She

Nick Lindert

Jakub Tadeusz Kedzierski

Xuejue Huang

By forming MOSFETs on a substrate having pre-existing ridges of semiconductor material (i.e., a 'corrugated substrate'), the resolution limitations associated with conventional semiconductor manufacturing processes can be overcome, and high-performance, low-power transistors can be reliably and repeatably produced. Forming a corrugated substrate prior to actual device formation allows the ridges on the corrugated substrate to be created using high precision techniques that are not ordinarily suitable for device production. MOSFETs that subsequently incorporate the high-precision ridges into their channel regions will typically exhibit much more precise and less variable performance than similar MOSFETs formed using optical lithography-based techniques that cannot provide the same degree of patterning accuracy. Additional performance enhancement techniques such as pulse-shaped doping and 'wrapped' gates can be used in conjunction with the segmented channel regions to further enhance device performance.

Integrated circuit on corrugated substrate

In fabricating a microelectromechanical structure (MEMS), a method of forming a narrow gap in the MEMS includes a) depositing a layer of sacrificial material on the surface of a supporting substrate, b) photoresist masking and at least partially etching the sacrificial material to form at least one blade of sacrificial material, c) depositing a structural layer over the sacrificial layer, and d) removing the sacrificial layer including the blade of the sacrificial material with a narrow gap remaining in the structural layer where the blade of sacrificial material was removed.

Damascene process for use in fabricating semiconductor structures having micro/nano gaps

A gated nano-electro-mechanical (NEM) switch employing metal-insulator-metal (MIM) technology and related devices and methods which can facilitate implementation of low-power, radiation-hardened, high-temperature electronic devices and circuits. In one example embodiment a gate electrode is configured as a cantilever beam whose free end is coupled to a MIM stack. The stack moves into bridging contact across a source and drain region when the applied gate voltage generates a sufficient electrostatic force to overcome the mechanical biasing of the cantilever beam. A second set of contacts can be added on the cantilever beam to form a complementary switching structure, or to a separate cantilever beam. The switching can be configured as non-volatile in response to stiction forces. NEM circuits provide a number of advantages within a variety of circuit types, including but not limited to: logic, memory, sleep circuits, pass circuits, and so forth.

Metal-insulator-metal (MIM) switching devices

Methods of designing an integrated circuit on corrugated substrate

A scalable nano-electro-mechanical memory cell design that requires only conventional semiconductor fabrication materials and surface micromachining technology, and is suited for use in cross-point memory arrays for very high density non-volatile storage. This design also leverages well established surface-micromachining technology and electro-mechanical device phenomena to achieve an elegantly simple and scalable memory cell structure that can potentially operate with low voltage. An elongate beam is held between a non-deflected state and a deflected state, or between two deflected states, therein defining two binary memory states. Stiction, buried charge layers, or a combination of stiction and buried charge layers can be incorporated to modify the stability of one or both deflected states for the cell. Current through the moveable portion of the elongate beam within the memory cell can be registered utilizing one or more access transistors for reading the data state.

Nano-electro-mechanical memory cells and devices

Performance of a complementary metal-oxide-semiconductor (CMOS) device having n-channel MOS transistors and p-channel MOS transistors is enhanced by providing a single capping layer overlying the MOS transistors with the single capping layer inducing stress in the transistor channel regions to enhance carrier mobility. The n-channel transistor is preferably fabricated in silicon having a (100) crystalline channel surface orientation, and the p-channel transistor is preferably fabricated in silicon having a (110) channel surface crystalline orientation. A tensile stress in the single capping layer induces tensile stress in the channel of the (100) n-channel transistor thereby enhancing the mobility of electrons while tensile stress in the single capping layer induces compressive stress in the channel of the (110) p-channel transistor thereby enhancing the mobility of holes. Alternatively, the n-channel transistor is fabricated in silicon having a (110) crystalline channel surface orientation, and the p-channel transistor is fabricated in silicon having a (100) channel surface crystalline orientation. A compressive stress in the single capping layer induces tensile stress in the channel of the (110) n-channel transistor thereby enhancing the mobility of electrons while compressive stress in the single capping layer induces compressive stress in the channel of the (100) p-channel transistor thereby enhancing the mobility of holes.

Complementary field-effect transistors having enhanced performance with a single capping layer

Charge migration in a SONOS memory cell is eliminated by physically separating nitride layer storage sites with dielectric material. Increased storage in a cell is realized with a double gate structure for controlling bit storage in line channels between a source and a drain, such as with a FinFET structure in which the gates are folded over the channels on sides of a fin.

Two bit/four bit SONOS flash memory cell

A variety of processes are disclosed for controlling NDR characteristics for an NDR element, such as peak-to-valley ratio (PVR), NDR onset voltage (V) and related parameters. The processes are based on conventional semiconductor manufacturing operations so that an NDR device can be fabricated using silicon based substrates and along with other types of devices.

Process for controlling performance characteristics of a negative differential resistance (NDR) device

A memory cell includes a storage capacitor and a negative differential resistance (NDR) field effect transistor (FET), wherein the NDR FET is connected between a high voltage source and the storage capacitor. A junction between the NDR FET and the storage capacitor forms a storage node of the memory cell. when a logic HIGH value is stored at the storage node, a pulsed gate bias signal turns on the NDR FET. In contrast, when a logic LOW value is stored at the storage node, the pulsed gate bias signal does not turn on the NDR FET. Thus, using the NDR FET as a pull-up element, the memory cell can exhibit a refresh behavior that is dependent on the data value stored in the memory cell. Moreover, this memory cell can be operated without a separate refresh cycle.

Negative differential resistance field effect transistor for implementing a pull up element in a memory cell

A static random access memory (SRAM) cell includes a SRAM circuit and a programmable resistor connected to a storage node of the SRAM circuit. The SRAM circuit can be any type of SRAM circuit, such as a 3T, negative differential resistance (NDR) transistor-based circuit, or a 6T (conventional SRAM) circuit. The programmable resistor can be formed in a metal layer above the SRAM circuit to minimize the area requirements for the memory cell. Just before shutdown of the SRAM cell, the resistance state of the programmable resistor is changed (if necessary) based on the data value stored at the storage node. The programmable resistor provides a non-volatile indication of the stored data value at the time of power off. Then, when power is restored to the SRAM cell, a data value based on the resistance state of the programmable resistor is written back into the SRAM circuit.

Compact static memory cell with non-volatile storage capability

Method of IC production using corrugated substrate

A method of controlling a negative differential resistance (NDR) element is disclosed, which includes altering various NDR characteristics during operation to effectuate different NDR modes. By changing biasing conditions applied to the NDR element (such as a silicon based NDR FET) a peak-to-valley ratio (PVR) (or some other characteristic) can be modified dynamically to accommodate a desired operational change in a circuit that uses the NDR element. In a memory or logic application, for example, a valley current can be reduced during quiescent periods to reduce operating power. Thus an adaptive NDR element can be utilized advantageously within a conventional semiconductor circuit.

Method of making adaptive negative differential resistance device

Segmented channel MOS transistor

Growing community of inventors

Fremont, CA, United States of America

Tsu-Jae King