International Business Machines Corporation

Taiwan Semiconductor Manufacturing Comp. Ltd.

TSMC Solid State Lighting Ltd.

Tsorng-Dih Yuan

Louis L Hsu

Hsin-Yu Pan

Lawrence Alfred Clevenger

Li-Kong Wang

Lawrence Shungwei Mok

Klaus D Beyer

Chang-Ming Hsieh

Chung-Yi Lin

Ching-Yu Ni

Jack Allan Mandelman

Carl John Radens

Rajiv V Joshi

Kim Hong Chen

Christy Sensenich Tyberg

Clinton Chao

Gaetano Paolo Messina

Mark Shane Peng

Tjandra Winata Karta

The present disclosure provides systems and methods for forming a semiconductor device. The semiconductor device includes a substrate having a first side and a second side opposite the first side. A first heat producing element is formed on the first side of the substrate. A second heat producing element is formed on the first side of substrate co-planar with, but not touching the first heat producing element. A heat spreader is coupled to the second side of the substrate using a thermal interface material. The heat spreader includes a first and second vapor chambers. The first vapor chamber is embedded in the heat spreader substantially opposite the first heat producing element. The second vapor chamber is embedded in the heat spreader substantially opposite the second heat producing element. As an example, the first heat producing element may be a light-emitting diode (LED) and the second heat producing element may be a driver circuit for the LED.

Thermal management system for multiple heat source devices

A flip chip semiconductor package is provided. In one embodiment, the flip chip semiconductor package comprises a first substrate having a first surface and a second surface opposite the first surface, a semiconductor chip mounted on the first surface of the first substrate by solder bumps, a thermally-conductive stiffener mounted above the first surface of the first substrate and around the chip to define a cavity region therebetween, one or more molding compound material disposed in the cavity region, and a second substrate mounted to the second surface of the first substrate by solder balls.

Flip chip package having enhanced thermal and mechanical performance

A stacked structure includes a first die coupled to a first substrate and having a first conductive structure formed through the first die. A second die is mounted over the first die. The second die is coupled to the first substrate by the first conductive structure. At least one first support structure formed from a second substrate is provided over the first substrate, adjacent to at least one of the first die and the second die. A top surface of the first support structure is substantially coplanar with a top surface of at least one of the first and second dies adjacent to the first support structure. The stacked structure further includes a heat spreader mounted over the second die.

Stacked structures and methods of fabricating stacked structures

A semiconductor package assembly is presented. The assembly comprises a first chip and a second chip. The back surfaces of the first and the second chips are thermally attached through a die attach material. The front surface of the first chip is attached to a substrate through bumps. A heat spreader extends from a surface of the semiconductor package assembly into the semiconductor package assembly and thermally attaches to the back surface of the first chip or the front surface of the second chip. Depending on the sizes of the chips and the location of the bonding pads, the heat spreader may be attached to the back surface of the first chip or the front surface of the second chip.

Heat stud for stacked chip package

Described are semiconductor package devices with improved reliability and methods of manufacturing thereof. In one embodiment, a package device is disclosed that includes a chip having an active surface and a coupling surface opposite the active surface, where the chip has one or more integrated circuits and bumps. The device also includes a thermal spreader thermally coupled to the coupling surface of the chip for dissipating heat generated by the chip, and a thermal interface material located between the thermal spreader and the coupling surface of the chip for improving the heat dissipation. In addition, the device also includes a boundary material located between the thermal spreader and the coupling surface of the chip, where the boundary material is configured to surround a perimeter of the thermal interface material to maintain the thermal interface material between the thermal spreader and the coupling surface of the chip.

Semiconductor packages and methods of manufacturing thereof

A process for fabricating a low dielectric constant semiconductor comprising the steps of: depositing a first metal layer on a substrate; patterning the first metal layer to produce a patterned first metal wiring; applying a first insulating material onto the patterned first metal wiring to form a support structure; patterning the first insulating material by a contact printing process; depositing a second insulating material of lower dielectric constant onto the support structure; planarizing the second insulating material; depositing a polish-stop film layer over the planarized second insulating material, thereby forming a plurality of metal studs; depositing a second metal layer onto the polish-stop film layer forming interconnects with said studs; and patterning the metal layer to produce a second metal wiring interconnecting to the first wiring via the metal studs.

Low dielectric semiconductor device and process for fabricating the same

An integrated circuit package comprises a semiconductor die located on a substrate in a flip-chip configuration, an encapsulant layer overlying the non-active surface of the semiconductor die and at least a portion of the surface of the substrate adjacent the die, and a heat spreader comprising a thermally conductive material. The heat spreader directly interfaces to a top surface of the encapsulant layer overlying the die and the substrate. This package provides physical protection during handling and reduced die stress and warpage.

Structural design for flip-chip assembly

A two loop heat conversion system for high heat density planar devices in which high density heat in an area adjacent to a surface is transferred into a liquid cooling medium closed loop in a radiated heat to liquid heat transfer component positioned in contact with the surface that is connected, to a liquid to gas medium, heat exchanger in a first loop and a gas medium second loop is arranged to carry away all radiated heat from the assembly and all heat extracted from the liquid in the liquid to gas heat exchanger and exhaust it to the ambient. The radiated heat transfer component of the invention provides a transition in manufacturing that is practiced employing the planar type tools in fabrication which usually can neither be practiced manually or observed without substantial magnification.

Increased efficiency in liquid and gaseous planar device cooling technology

Thermal cooling structures of diamond or diamond-like materials are provided for conducting heat away from semiconductor devices. A first silicon-on-insulator embodiment comprises a plurality of thermal paths, formed after shallow trench and device fabrication steps are completed, which extend through the buried oxide and provide heat dissipation through to the underlying bulk silicon substrate. The thermal conduction path material is preferably diamond which has high thermal conductivity with low electrical conductivity. A second diamond trench cooling structure, formed after device fabrication has been completed, comprises diamond shallow trenches disposed between the devices and extending through the buried oxide layer. An alternative diamond thermal cooling structure includes a diamond insulation layer deposited over the semiconductor devices in either an SOI or bulk silicon structure. Yet another embodiment comprises diamond sidewalls formed along the device walls in thermal contact with the device junctions to provide heat dissipation through the device junctions to underlying cooling structures. It is also proposed that the foregoing structures, and combinations of the foregoing structures, could be used in conjunction with other known cooling schemes.

Method and structure for providing improved thermal conduction for silicon semiconductor devices

A cooling device having a common cooling distribution unit with multiple compliant cooling elements. Mechanisms are built in to ensure the cooling elements are in good thermal contact with heat generating semiconductor chips of different heights and sizes on a common carrier. The cooling distribution unit has protection structures to prevent the leakage of coolant from the unit. Further reduction of the risk of accidental coolant leakage is provided with the onboard storage of coolant absorbent materials in the coolant distribution unit. The cooling elements have serpentine coolant channels to enhanced the cooling capacity. The compliance of the cooling elements can also be achieved by using concentric tubing to connect the coolant distribution unit to cooling heads on the cooling elements.

Cooling device with multiple compliant elements

The present invention provides for globally aligning microelectronic circuit systems, such as communication devices and chips, fabricated on or bonded to the front and back sides of one or more substrates to provide for wireless communications between the circuit systems through the one or more substrates. In one embodiment, two circuit systems situated on opposite sides of a substrate are aligned to provide for wireless communications between the two circuit systems through the substrate. In another embodiment, communication devices situated on one or more substrates are aligned to provide for wireless communications between the communication devices through the one or more substrates. In another embodiment, two chips situated on opposite sides of a transparent substrate are aligned to provide for wireless communications between the two chips through the transparent substrate.

Semiconductor device utilizing alignment marks for globally aligning the front and back sides of a semiconductor substrate

A chip packaging system and method for providing enhanced thermal cooling including a first embodiment wherein a diamond thin film is used to replace at least the surface layer of the existing packaging material in order to form a highly heat conductive path to an associated heat sink. An alternative embodiment provides diamond thin film layers disposed on adjacent surfaces of the chip and the chip package. Yet another alternative embodiment includes diamond thin film layers on adjacent chip surfaces in a chip-to-chip packaging structure. A final illustrated embodiment provides for the use of an increased number of solder balls disposed in at least one diamond thin film layer on at least one of a chip and a chip package joined with standard C4 technology.

Chip packaging system and method using deposited diamond film

A wafer structure and a method of making the same, upon which semiconductor devices may be formed, comprises first and second wafers. The first wafer comprises a first substrate having a thin oxide layer formed on a bottom surface thereof, the first substrate having a characteristic thermal expansion coefficient. The second wafer comprises a second substrate having an insulation layer formed on a top surface thereof, the insulation layer having a characteristic thermal expansion coefficient substantially matched with the characteristic thermal expansion coefficient of the first substrate and further having a high thermal conductivity. The second wafer further comprises a thin oxide layer formed on a top surface of the insulation layer, wherein the first thin oxide layer of the first wafer is bonded to the second thin oxide layer of the second wafer.

Growing community of inventors

Hsinchu, Taiwan

Tsorng-Dih Yuan