Mellanox Technologies, Ltd.

Tsofia Eshel

Mark B Rosenbluth

Ilan Pardo

Idan Burstein

Oded Lempel

Rui Xu

Amir Rosen

In one embodiment, a computer system includes a payload sub-system including interfaces to connect with respective devices, transfer data with the respective devices, and receive write transactions from the respective devices, a classifier to classify the received write transactions into payload data and control data, and a payload cache to store the classified payload data, and a processing unit (PU) sub-system including a local PU cache to store the classified control data, wherein the payload cache and the local PU cache are different physical caches in respective different physical locations in the computer system, and processing core circuitry configured to execute software program instructions to perform control and packet processing responsively to the control data stored in the local PU cache.

Payload cache

An apparatus includes multiple processors, a classifier and queue management logic. The classifier is configured to classify tasks, which are received for execution by the processors, into multiple processor queues, each processor queue associated with a single processor or thread, and configured to temporarily store task entries that represent the tasks, and to send the tasks for execution by the associated processors. The queue management logic is configured to set, based on queue-lengths of the queues, an affinity strictness measure that quantifies a strictness with which the tasks of a same classified queue are to be processed by a same processor, and to assign the task entries to the queues while complying with the affinity strictness measure.

Multi-processor queuing model

Growing community of inventors

Eshchar, Israel

Tsofia Eshel