International Business Machines Corporation

Globalfoundries Inc.

Tso-Hui Ting

Ping-Chuan Wang

Yunsheng Song

Oleg Gluschenkov

Yongchun Xin

Louis V Medina

Xu Ouyang

Robert Daniel Edwards

Muthukumarasamy Karthikeyan

Richard Paul Volant

Brian M Trapp

Edward J Crawford

Mohammed I Younus

A test structure for an integrated circuit device includes a series inductor, capacitor, resistor (LCR) circuit having one or more inductor elements, with each inductor element having at least one unit comprising a first segment formed in a first metal layer, a second segment connecting the first metal layer to a semiconductor substrate beneath the first metal layer, and a third segment formed in the semiconductor substrate; and a capacitor element connected in series with each inductor element, the capacitor element defined by a transistor gate structure including a gate electrode as a first electrode, a gate dielectric layer, and the semiconductor substrate as a second electrode.

LCR test circuit structure for detecting metal gate defect conditions

A wafer probing system includes a probe card assembly having a plurality of individual probe structures configured make contact with a semiconductor wafer mounted on a motor driven wafer chuck, with each probe structure configured with a pressure sensing unit integrated therewith; and a controller configured to drive the probe card assembly with one or more piezoelectric driver units response to feedback from the pressure sensing units of the individual probe structures.

Semiconductor wafer probing system including pressure sensing and control unit

A modularized interposer includes a plurality of interposer units that are assembled to provide a complete set of electrical connections between two semiconductor chips. At least some of the plurality of interposer units can be replaced with other interposer units having an alternate configuration to enable selection of different functional parts of semiconductor chips to be connected through the modularized interposer. Bonding structures, connected to conductive metal pads located at peripheries of neighboring interposer units and an overlying or underlying portion of a semiconductor chip, can provide electrical connections between the neighboring interposer units. The interposer units can be provided by forming through-substrate vias (TSV's) in a substrate, forming patterned conductive structures on the substrate, and cutting the substrate into interposers.

Configurable interposer

Pressure sensing and control for semiconductor wafer probing

A set of first substrate and second substrate are manufactured with a built-in N-fold rotational symmetry around the center axis of each substrate, wherein N is an integer greater than 1. A set of N different interposers is provided such that an i-th interposer provides electrical connection between the first substrate and the second substrate with a rotational angle of (i&#x2212;1)/N&#xd7;2&#x3c0;. The first and second substrates are tested with each of the N different interposers therebetween. Once the rotational angle that provides the highest stacked chip yield is determined, the first and the second substrates can be bonded with an azimuthal rotation that provides the highest stacked chip yield.

Yield enhancement for stacked chips through rotationally-connecting-interposer

An on-chip technique for noncontact electrical testing of a test structure on a chip is provided. On-chip photodiodes receives pump light from a pump light source, where the on-chip photodiodes are electrically connected to the test structure and are configured to generate power for the test structure. An on-chip coupling unit receives probe light from a probe light source, where the on-chip coupling unit is optically connected to on-chip waveguides through which the probe light is transferred. On-chip switches open in response to receiving voltage output from the test structure, and the on-chip switches remain closed when the voltage output is not received from the test structure. The on-chip switches pass the probe light when opened by the voltage output from the test structure. The on-chip switches block the probe light by remaining closed, when the voltage output is not received from the test structure.

Noncontact electrical testing with optical techniques

A system for performing alignment of two wafers is disclosed. The system comprises an optical coherence tomography system and a wafer alignment system. The wafer alignment system is configured and disposed to control the relative position of a first wafer and a second wafer. The optical coherence tomography system is configured and disposed to compute coordinate data for a plurality of alignment marks on the first wafer and second wafer, and send that coordinate data to the wafer alignment system.

Wafer alignment system with optical coherence tomography

A system and a method are provided. The method includes assigning an entity to a ticket group associated with an ID thereof, displaying to the entity reports, which are each organized with an associated security access control, in accordance with the ticket group, determining whether the entity is authorized to access any selected one or more of the reports in accordance with a result of a comparison between an access level associated with the entity ID and the security access control associated with each of the one or more of the stored reports, and granting or denying the access in accordance with the determination.

Security control of analysis results

An apparatus is provided and includes a thermally isolated device under test to which first and second voltages are sequentially applied, a local heating element to impart first and second temperatures to the device under test substantially simultaneously while the first and second voltages are sequentially applied, respectively and a temperature-sensing unit to measure the temperature of the device under test.

In-line characterization of a device under test

A method of establishing a lot grading system for lots in a semiconductor manufacturing process includes defining a new lot grade for at least one lot in the semiconductor manufacturing process. The at least one lot is has a current lot grade and the new lot grade is dependent upon the current lot grade. The new lot grade is saved in a grading referenced database and the at least one lot in the semiconductor manufacturing process is updated with the new lot grade.

Method of establishing a lot grade system for product lots in a semiconductor manufacturing process

A system and a method for effectively determining the measurement sensitivity, repeatability, and probe commonality to assist a test engineer determine if the tester meets the specified resolution at every test. A statistical measurement of inherent tester specifications are provided with the added accumulation of the probe contact resistance during the probing process. It further provides a feedback to the test probe card noise level while testing is in progress. Moreover, the system and the method determine the test probing integrity in-situ when testing integrated circuit chips or wafers, dynamically detecting probing errors, and modifying data associated with defective test probes.

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Stormville, NY, United States of America

Tso-Hui Ting