Winbond Electronics Corporation

Tso-Hua Hung

Ching-Ya Huang

Bo-Lun Wu

Kao-Tsair Tsai

Ting-Ying Shen

Hsaio-Yu Lin

A method for measuring critical dimension is provided. The method includes the steps of: receiving a critical-dimension scanning electron microscopy (CD-SEM) image of a semiconductor wafer; performing an image-sharpening process and an image de-noise process on the CD-SEM image to generate a first image; performing an edge detection process on the first image to generate a second image; performing a connected-component labeling process on the second image to generate an output image; and calculating a critical-dimension information table of the semiconductor wafer according to the output image.

Method for measuring critical dimension and image-processing apparatus for measuring critical dimension

A recognition method of pattern feature is provided, where a recognition result thereof is applied to optical proximity correction, the method includes: providing a plurality of reference images with a reference pattern feature; recognizing and classifying the reference images by an image recognition device, and storing the recognition result; comparing the image with the actual pattern feature with the stored recognition result by the image recognition device to recognize and classify the image with the actual pattern feature; and calculating an angle feature value and/or a distance feature value of the actual pattern feature by the image recognition device according to a classification result to obtain the recognition result of the pattern feature.

Recognition method of pattern feature

Memory devices are provided. The memory device includes a substrate. A dielectric layer is disposed on the substrate and a plurality of resistive memory cells is disposed on the dielectric layer. Each resistive memory cell includes a via disposed in a first opening of the dielectric layer. A conductive layer is disposed on the via. The memory device further includes a capacitor structure including a bottom electrode, a variable resistance layer disposed on the bottom electrode and a top electrode disposed on the variable resistance layer, wherein the bottom electrode is disposed on the conductive layer.

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Taichung, Taiwan

Tso-Hua Hung