Stmicroelectronics Gmbh

Sgs-thomson Microelectronics Limited

Mostek Corporation

Other

Thomson Components-mostek Corporation

Tsiu Chiu Chan

Frank R Bryant

Melvin Joseph DeSilva

Loi Ngoc Nguyen

Yu-Pin Han

Elmer H Guritz

Gregory C Smith

Mehdi Zamanian

Kuei-Wu Huang

Pervez Hassan Sagarwala

Lawrence Philip Eng

William A Bishop

Richard Ferrant

Artur P Balasinski

Jason Siucheong So

Vernon G McKenny

John L Walters

David S Culver

Richard A Blanchard

David C McClure

Anthony M Chiu

Che-Chia Wei

James Brady

Lun-Tseng Lu

Syama Sundar Sunkara

Jamin Ling

Jim Brady

Arnaud Lepert

Lisa K Jorgenson

Fu-Tai Liou

Herman H Ma

Antonio Imbruglia

Thi N Nguyen

Chao C Mai

Vernon C McKenny

Myint Hswe

An SRAM memory cell having first and second transfer gate transistors. The first transfer gate transistor includes a first source/drain connected to a bit line and the second transfer gate transistor has a first source/drain connected to a complement bit line. Each transfer gate transistor has a gate connected to a word line. The SRAM memory cell also includes first and second pull-down transistors configured as a storage latch. The first pull-down transistor has a first source/drain connected to a second source/drain of said first transfer gate transistor; the second pull-down transistor has a first source/drain connected to a second source/drain of said second transfer gate transistor. Both first and second pull-down transistors have a second source/drain connected to a power supply voltage node. The first and second transfer gate transistors each include a gate oxide layer having a first thickness, and the first and second pull-down transistors each include a gate oxide layer having a second thickness, wherein and the first thickness is different from the second thickness.

Structure for transistor devices in an SRAM cell

An apparatus and method for fabricating a microprocessor comprising a first chip () having an active face () including a central processing unit and a second chip () having an active face () electrically connected to the active face of the first chip (), wherein the second chip () provides added functionality to the central processing unit of the first chip () and wherein the electrical connections () are through bonding layers () that are in contact with the metalization 26 on the first and second chips (), is disclosed.

Stacked multi-component integrated circuit microprocessor

An apparatus and method for fabricating-a microprocessor comprising a first chip () having an active face () including a central processing unit and a second chip () having an active face () electrically connected to the active face of the first chip (), wherein the second chip () provides added functionality to the central processing unit of the first chip () and wherein the electrical connections () are through bonding layers () that are in contact with the metalizationon the first and second chips (), is disclosed.

A random access memory cell and fabrication method therefor are disclosed. The random access memory cell includes a first and a second pull-down transistor cross-coupled such that a control terminal of the first pull-down transistor is connected to a conduction terminal of the second pull-down transistors, and the control terminal of the second pull-down transistor is connected to the conduction terminal of the first pull-down transistor. A first pass gate transistor is coupled between the conduction terminal of the first transistor and a first bit line of a bit line pair, and a second pass gate transistor is coupled between the conduction terminal of the second transistor and a second bit line of the bit line pair. The threshold voltage of the first and second pass gate transistors is such that a subthreshold current is provided to the first and second pull-down transistors when the memory cell is not being accessed such that the conduction terminal of the pull-down transistor that is turned off is maintained at a voltage level corresponding to a logic high voltage. In this way, the memory cell is capable of performing a latching function without pull-up transistors.

Random access memory cell and method for fabricating same

An integrated circuit and method are provided for sensing activity such as acceleration in a predetermined direction of movement. The integrated released beam sensor preferably includes a switch detecting circuit region and a sensor switching region connected to and positioned adjacent the switch detecting circuit region. The sensor switching region preferably includes a plurality of floating contacts positioned adjacent and lengthwise extending outwardly from said switch detecting circuit region for defining a plurality of released beams so that each of said plurality of released beams displaces in a predetermined direction responsive to acceleration. The plurality of released beams preferably includes at least two released beams lengthwise extending outwardly from the switch detecting circuit region to different predetermined lengths and at least two released beams lengthwise extending outwardly from the switch detecting circuit region to substantially the same predetermined lengths. The methods of forming an integrated sensor advantageously are preferably compatible with know integrated circuit manufacturing processes, such as for CMOS circuit manufacturing, with only slight variations therefrom.

Integrated sensor having plurality of released beams for sensing acceleration and associated methods

A radiation hardened memory device having static random access memory cells includes active gate isolation structures to prevent leakage currents between active regions formed adjacent to each other on a substrate. The active gate isolation structure includes a gate oxide and polycrystalline silicon gate layer electrically coupled to a voltage terminal resulting in an active gate isolation structure that prevents a conductive channel extending from adjacent active regions from forming. The gate oxide of the active gate isolation structures is relatively thin compared to the conventional oxide isolation regions and thus, will be less susceptible to any adverse influence from trapped charges caused by radiation exposure.

Radiation hardened semiconductor memory

A method is provided for forming an improved contact opening of a semiconductor integrated circuit, and an integrated circuit formed according to the same. Planarization of the semiconductor structure is maximized and misalignment of contact openings is tolerated by first forming a conductive structure over a portion of a first body. A thin dielectric layer is formed at least partially over the conductive structure. A thick film, having a high etch selectivity to the thin dielectric layer, is formed over the dielectric layer. The thick film is patterned and etched to form a stack substantially over the conductive structure. An insulation layer is formed over the thin dielectric layer and the stack wherein the stack has a relatively high etch selectivity to the insulation layer. The insulation layer is etched back to expose an upper surface of the stack. The stack is then etched to form an opening in the insulation layer exposing the thin dielectric layer which acts as an etch stop during the stack etch process. The thin dielectric layer is then etched in the opening to expose the first conductive layer. A conductor is then formed in the opening contacting the underlying conductive structure. The thin dielectric under the insulation layer and on the sides of the opening near the conductive structure will increase the distance and help to electrically isolate the conductor at the edge of the contact opening from nearby active areas and devices.

Contact in an integrated circuit

A memory cell for an EEPROM memory is fabricated to provide increased oxide thickness at the edge of the tunnel oxide and under the edges of the polysilicon capacitor plate in order to improve the dielectric integrity of the capacitor structure. In one embodiment using a silicided polysilicon process, the oxide is made thicker at the edge of the tunnel oxide by reoxidizing the silicon at the corner of the polysilicon capacitor plate and the underlying substrate surface by exposing the device to a short duration oxidation step after having deposited a 200 &angst; to 500 &angst; thick porous oxide over the device to protect the silicide from excessive exposure to the oxidizing ambient. In another embodiment the tunnel oxide is grown in a window in the gate oxide layer, which is about four times thicker than the tunnel oxide, so that the gate oxide completely surrounds the tunnel oxide, and the polysilicon capacitor plate extends beyond the edge of the tunnel oxide terminating at a point above the gate oxide.

EEPROM memory cell with increased dielectric integrity

A method is disclosed for a memory cell for a static random access memory. The memory cell includes a pair of cross-coupled CMOS logic inverters that are connected together to form a latch, and a pair of p-channel transmission gate transistors that are connected to the logic inverters for selectively providing access to the latch. The layout of the memory cell includes a rectangular active area in which the p-channel transistors of the memory cell are located. The rectangular active area abuts a similar active area of an adjacent memory cell along a row of memory cells so as to form a single rectangular active area for the p-channel memory cell transistors. The rectangular active area reduces the occurrence of fabrication-related phenomena that adversely effect the performance of the memory cell.

Method of fabricating a memory cell for a static random access memory

A radiation hardened memory device includes active gate isolation structures placed in series with conventional oxide isolation regions between the active regions of a memory cell array. The active gate isolation structure includes a gate oxide and polycrystalline silicon gate layer electrically coupled to a voltage potential resulting in an active gate isolation structure that prevents a conductive channel extending from adjacent active regions from forming. The gate oxide of the active gate isolation structures is relatively thin compared to the conventional oxide isolation regions and thus, will be less susceptible to any adverse influence from trapped charges caused by radiation exposure.

Radiation hardened semiconductor memory with active isolation regions

Silver interconnects are formed by etching deep grooves into an insulating layer over the contact regions, exposing portions of the contact regions and defining the interconnects. The grooves are etched with a truncated V- or U-shape, wider at the top than at any other vertical location, and have a minimum width of 0.25 &mgr;m or less. An optional adhesion layer and a barrier layer are sputtered onto surfaces of the groove, including the sidewalls, followed by sputter deposition of a seed layer. Where aluminum is employed as the seed layer, a zincating process may then be optionally employed to promote adhesion of silver to the seed layer. The groove is then filled with silver by plating in a silver solution, or with silver and copper by plating in a copper solution followed by plating in a silver solution. The filled groove which results does not exhibit voids ordinarily resulting from sputter deposition of metal into such narrow, deep grooves, although seams may be intermittently present in portions of the filled groove where metal plated from the opposing sidewalls did not fuse flawlessly at the point of convergence. Portions of the silver and other layers above the insulating material are then removed by chemical-mechanical polishing, leaving a silver interconnect connected to the exposed portion of the contact region and extending over adjacent insulating regions to another contact region or a bond pad. Silver interconnects thus formed may have smaller cross-sections, and thus a greater density in a given area, than conventional metallic interconnects.

Silver metallization by damascene method

A redundant electric fuse circuit is provided that includes a plurality of fuses coupled in series and each having a fuse control device operable for generating a current through each fuse sufficient to blow the fuse. A first fuse control signal is activated to generate a sufficient current through one of the fuses to blow the fuse. A second fuse control signal is activated to generate a sufficient current through the other fuse to blow that fuse. The electric fuse circuit provides redundancy thereby increasing the yield of integrated circuits by reducing the probability that a defective fuse (i.e., a fuse that reforms after blowing) will cause a fatal defect in the integrated circuit.

Redundant electric fuses

Method of forming a contact in an integrated circuit

Growing community of inventors

Carrollton, TX, United States of America

Tsiu Chiu Chan