Tsinghua University

Tsin-Yuan Chang

Ming-Jun Hsiao

Shao-Sheng Yang

Shu-Rong Lee

Hao-Yung Lo

Jing-Reng Huang

In a method and apparatus for controlling a dual-slope integrator circuit, a reset signal is provided to a reset input of the integrator circuit to maintain a reset state of an integrating capacitor for a predetermined reset time period in response to an original input signal. A delayed input signal is simultaneously generated by introducing a predetermined delay period into the original input signal, the delay period being longer than the reset time period. With reference to the original input signal and the delayed input signal, a trigger signal is provided to an integrator input of the integrator circuit for enabling charging operation of the integrating capacitor during a charging period that starts from the end of the reset time period and that terminates at a lagging edge of the delayed input signal.

Method and apparatus for controlling a dual-slope integrator circuit to eliminate settling time effect

An integrated circuit device includes an embedded memory, a built-in self-test (BIST) circuit, an access time measuring circuit, and a built-in detecting circuit. The BIST circuit is coupled electrically to the memory, and is operable so as to perform consecutive test operations upon addressable memory locations of the memory. The access time measuring circuit is coupled electrically to the memory and the BIST circuit, and is operable so as to generate an access time signal corresponding to access time of one of the memory locations that is currently being tested by the BIST circuit. The detecting circuit is coupled electrically to the measuring circuit, monitors a maximum value of the access time signals generated by the measuring circuit during the consecutive test operations, and outputs a maximum access time signal upon completion of the consecutive test operations.

Integrated circuit device with a built-in detecting circuit for detecting maximum memory access time of an embedded memory

A feedback latch circuit includes a first logic OR gate for performing a logic OR operation upon a clock input signal and a latch output, a first logic AND gate for performing a logic AND operation upon output of the first logic OR gate and a data input signal, a second logic AND gate for performing a logic AND operation upon a complementary clock input signal and the latch output, and a second logic OR gate for performing a logic OR operation upon outputs of the first and second logic AND gates to result in the latch output that is provided to the first logic OR gate and the second logic AND gate. The complementary clock input signal received by the second logic AND gate complements the clock input signal received by the first logic OR gate.

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Hsinchu, Taiwan

Tsin-Yuan Chang