Hitachi, Ltd.

Tshiaki Tarui

Naonobu Sukegawa

Hiroaki Fujii

Hideya Akashi

A parallel processor system controls access to a distributed shared memory and to plural cache memories to prevent frequently-used local data from being flushed out of a cache memory. The parallel processor system includes a plurality of nodes each including a processor and a shared memory in a distributed shared memory arrangement, and a local-remote divided cache memory system, wherein local data and remote data are controlled separately. Each local-remote divided cache memory system includes a local data area, a remote data area, and a cache memory controller by which either the local data area or the remote data area is accessed according to the contents of an access request.

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Kokubunji, Japan

Tshiaki Tarui