Integrated Device Technology, Inc.

Tsengyou Syau

Shih-Ked Lee

Chuen-Der Lien

Kuilong Wang

Jeong Yeol Choi

Sang-Yun Lee

Guo-Qiang Lo

Guo-Qiang (Patrick) Lo

Ohm-Guo Pan

James R Shih

Yu-Lung Mao

Ching-Kai (Robert) Lin

Timothy P Kay

Zhenjiang Yu

A method for forming CMOS devices on a semiconductor substrate is disclosed in which gate structures are formed within both the core region and the non-core region of the semiconductor substrate. The gate structures include a gate dielectric layer and a gate film stack that includes a conductive layer and an overlying hard mask. The hard mask is then removed from the gate structures in the non-core region. A salicide process is then performed so as to form a silicide layer in the non-core region. A barrier layer is formed that extends over the core region and a pre-metal dielectric film is formed that extends over the barrier layer. A selective etch process is performed so as to form self-aligned contact openings that extend through the pre-metal dielectric film and through the barrier layer in the core region. These openings are then filled with conductive material to form self-aligned contacts in the core region. This produces a CMOS device in the core region that has high device density and includes high-speed CMOS devices the non-core region.

Method for forming CMOS device with self-aligned contacts and region formed using salicide process

A method for preventing the formation of watermark defects includes the steps of forming a pad oxide, a silicon nitride layer and a silicon oxynitride layer over a semiconductor substrate. A photoresist mask is formed over the resulting structure, with the silicon oxynitride layer being used as an anti-reflective coating during exposure of the photoresist material. An etch is performed through the photoresist mask, thereby forming a trench in the substrate. The photoresist mask is stripped, and the silicon oxynitride layer is conditioned. For example, the silicon oxynitride layer may be conditioned by a rapid thermal anneal in the presence of oxygen or nitrogen. A wet clean step is subsequently performed to remove a native oxide layer in the trench. The conditioned silicon oxynitride layer prevents the formation of watermarks during the wet clean process.

Dielectric anti-reflective coating surface treatment to prevent defect generation in associated wet clean

A method for forming self-aligned contact devices in a core region of a semiconductor substrate and non-self-aligned contact devices in a non-core region of the semiconductor substrate is disclosed in which a single gate film stack is used for forming gate structures in both the core region and in the non-core region. A dielectric layer is formed over a semiconductor substrate and a gate film stack is formed over the dielectric layer. The gate film stack is then patterned so as to form gate structures within both the core region and the non-core region.

Method for forming hybrid device gates

Method for forming cmos device with self-aligned contacts and region formed using salicide process

A CMOS structure and a process for forming CMOS devices are disclosed in which gate film stacks are formed over a semiconductor substrate. A barrier layer and a first dielectric film are formed such that they extend over the gate film stacks. Metal lines are formed over the pre-metal dielectric film and spacers are formed that extend on opposite sides of the metal lines. A second dielectric film is formed that extends over the metal lines. A masking structure is formed that defines a contact opening. Selective etch processes are performed to form a self-aligned contact opening, with the adjacent metal lines and spacers aligning the self-aligned contact opening between adjacent gate film stacks. A metal layer is then deposited and planarized to form a self-aligned contact. The masking structure can also define additional contact openings, which are simultaneously etched and filled with metal to form borderless, strapped and shared contacts. These borderless contacts, contacts and shared contacts can either be aligned on one side or can be positioned using only the masking structure.

Self-aligned contact structure and process for forming self-aligned contact structure

A novel gate structure and a method of forming the same for a self-aligned contact on a semiconductor substrate. The method includes forming a gate oxide layer on the semiconductor substrate. Then a first conductive layer is formed on the gate oxide layer. Next, a second conductive layer, preferably a refractory metal silicide (e.g. WSi ), is formed overlying the first conductive layer. A capping layer is formed overlying the second conductive layer. Then the capping layer is etched to form a patterned capping layer having a lower outside corner. An upper portion of the second conductive layer is selectively dry etched laterally to form a lateral recess under the capping layer to increase etch margin. A lower portion of the second conductive layer is then etched anisotropically down to the first conductive layer along a sidewall approximately vertically aligned with the lower outside corner of the patterned capping layer. The recess has an inward extant from the lower outside corner in a range of between 100-300 Angstroms. Increased etch margin is provided in the gate structure to prevent shorts between contact plugs and gate structures during contact formation.

Gate structures with increased etch margin for self-aligned contact and the method of forming the same

The invented method involves separately etching the P and N gate features in a dual-poly gate using dual masks, thereby permitting the etching recipes to be tuned to the differentially responsive P and N materials that form the gate. The method involves a) providing a polysilicon layer of a first type over a first region of a semiconductor substrate; b) providing a polysilicon layer of a second type over a second region of the semiconductor substrate; c) depositing a metallic layer overlying the polysilicon layers in the first and second regions; d) depositing an anti-reflective layer overlying the metallic layer in the first and second regions; e) selectively etching the dielectric hard-mask multi-layer film to form a patterned outer hard-mask multi-layer; f) forming a first photoresist pattern overlying the patterned outer hard-mask multi-layer in the first region; g) first etching the metallic layer and the polysilicon layer of the second type to form a stacked gate structure in the second region; h) forming a second photoresist pattern overlying the patterned outer hard-mask multi-layer in the second region; and i) second etching the metallic layer and the polysilicon layer of the first type to form a stacked gate structure in the first region. Preferably, the first photoresist pattern and the second photoresist pattern define a nominal boundary therebetween, with the patterns having a predefined gap therebetween in a region around the boundary. Alternatively, the dual-mask technique is used on a non-hardmask dual-poly film stack and the top dielectric multi-layer film is replaced by an anti-reflection coating (ARC) film.

Dual-mask etch of dual-poly gate in CMOS processing

The prevention of the formation of undesired defects formed during the etching of etched metal interconnect lines on an integrated circuit during an integrated circuit manufacturing process that involves laying down on a semiconductor wafer a thin film such as an anti-reflective coating (ARC) on a layer of metal to be patterned into the metal interconnects of the individual integrated circuits. To do this the anti-reflective coating layer is covered with an oxide layer prior to applying and patterning subsequent photoresist. The specific metalization layer disclosed can be of aluminum, copper or copper-aluminum alloy. The ARC as disclosed is a nitride layer, such as titanium nitride. The oxide may be formed on the ARC in a number of known ways and may be etched subsequently alone or in combination with the underlying ARC and metal after subsequent photoresist deposit upon the oxide layer.

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Portland, OR, United States of America

Tsengyou Syau