Macronix International Co., Ltd.

Macronix Internationalco., Ltd.

Tseng-Yi Liu

Shuo-Nan Hung

Chun-Hsiung Hung

Han-Sung Chen

Chun Hsiung Hung

Chia-Hsing Chen

Cheng-Jye Liu

Chung-Hsiung Hung

Chang Ting Chen

Chi-Yu Hung

Various aspects of a NAND memory include a control circuit that applies a read bias arrangement to a plurality of word lines to read a selected data value stored on a plurality of memory cells by measuring current flowing between the first end and the second end of the series of memory cells. The read bias arrangement is applied to word lines of the plurality of word lines applies only word line voltages less than a second maximum of a second threshold voltage distribution.

Method and apparatus for reducing read disturb in memory

An integrated circuit device has multiple blocks of NAND memory cells, and a high voltage switch. The high voltage switch is coupled to a decoder output and the blocks of NAND memory cells. The high voltage switch has an output voltage range with positive and negative voltages.

Decoder for NAND memory

Various aspects of a NAND memory include have multiple versions of a high threshold voltage distribution&#x2014;a version with a reduced maximum, and another version. The version with a reduced maximum has a reduced word line pass voltage.

An on-the-fly repair method for a memory includes: performing a block erase operation on the memory; checking whether the block erase operation is passed or not; finding whether there is any available and healthy redundancy block in the memory if the block erase operation is not passed; programming an address of a failed block to be repaired, an enable bit and at least one error correction bit into both first and second redundancy information regions in a redundancy information set of the memory; checking whether error in the first and the second redundancy information regions is recoverable based on the error correction bit; and if the error is recoverable, then programming the redundancy information set as effective to replace the failed block by the redundancy block related to the effective redundancy information set.

On-the-fly repair method for memory

A voltage regulating method applied to a memory to regulate a word line voltage corresponding to a set of memory cells of the memory includes the following steps. Firstly, a first value, which is for indicating an amount of data having a specific data value in a set of written data, is counted, wherein the set of written data is written into the set of memory cells. Next, a second value, which is for indicating an amount of data having the specific data value in a set of read data, is counted, wherein the set of read data is obtained by reading the set of written data. Then, a regulating voltage is determined according to a difference between the first and second values. After that, the word line voltage is regulated to be a sum of the word line voltage and the regulating voltage.

Voltage regulation method and memory applying thereof

A method for compensating a threshold voltage of a neighbor bit, are provided. The method includes the first step of arbitrating the word line voltages applied to bits demanded to be programmed, wherein the the word line voltages are arbitrated according to the threshold voltages of the neighbor bits adjacent to the bits. Next, the bits, to which a same word line voltage should be applied, in the memory cells are distributed to a group of bits with the same word line voltage. Then, the same word line voltage is applied to the bits of the group of bits with the same word line voltage.

Method for compensating a threshold voltage of a neighbor bit

An erase device and a method of erasing data from a flash memory. The erase device includes a shift control signal transmission terminal, an erase control group and a pulse control group. The shift control signal transmission terminal is used for transmitting a shift control signal. The erase control group includes a plurality of serially connected erase controllers. Each erase controller corresponds to a memory block. Each of the erase controllers contains a shift register, a receiving terminal and an output terminal. The receiving terminal of the first erase controller receives a shift control signal sent from the shift control signal transmission terminal. The receiver terminal of a subsequent erase controller connects electrically with the output terminal of the previous erase controller. In addition, the shift register contains a shift control signal received from the receiving terminal. The shift control signal is used for directing the erasure of memory block data that correspond to the erase controller. The pulse control signal group controls the sending and the receiving of shift control signals.

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Hsinchu, Taiwan

Tseng-Yi Liu