Taiwan Semiconductor Manufacturing Comp. Ltd.

Tseng Chin Lo

Bo-Sen Chang

Chih-Ting Sun

Molly Chang

Ya-Wen Tseng

Geng-He Lin

Zi-Kuan Li

Kung-Cheng Lin

Yueh-Yi Chen

Ying-Jung Chen

Meng Lin Chang

Chin-Hsiang Lin

Jong-I Mou

Shien-Yang Wu

Jui-Long Chen

Hui-yun Chao

Ta-Yung Lee

Chien-Chih Liao

Chien-Chang Lee

Yih-Yuh Doong

Kuo-Tsai Li

Jiing-Shin Shyu

Chih-Chieh Shao

Konrad Young

Integrated circuits and methods for overlap measure are provided. In an embodiment, an integrated circuit includes a plurality of functional cells including at least one gap disposed adjacent to at least one functional cell of the plurality of functional cells and a first overlay test pattern cell disposed within the at least one gap, wherein the first overlay test pattern cell includes a first number of patterns disposed along a first direction at a first pitch. The first pitch is smaller than a smallest wavelength on a full spectrum of humanly visible lights.

Method of measuring mask overlay using test patterns

Provided is a method for inserting a pre-designed filler cell, as a replacement to a standard filler cell, including identifying at least one gap among a plurality of functional cells. In some embodiments, a pre-designed filler cell is inserted within the at least one gap. By way of example, the pre-designed filler cell includes a layout design having a pattern associated with a particular failure mode. In various embodiments, a layer is patterned on a semiconductor substrate such that the pattern of the layout design is transferred to the layer on the semiconductor substrate. Thereafter, the patterned layer is inspected using an electron beam (e-beam) inspection process.

Integrated circuit filler and method thereof

Integrated circuit overlay test patterns and method thereof

A system and method for aligning a probe, such as a wafer-level test probe, with wafer contacts is disclosed. An exemplary method includes receiving a wafer containing a plurality of alignment contacts and a probe card containing a plurality of probe points at a wafer test system. A historical offset correction is received. Based on the historical offset correct, an orientation value for the probe card relative to the wafer is determined. The probe card is aligned to the wafer using the orientation value in an attempt to bring a first probe point into contact with a first alignment contact. The connectivity of the first probe point and the first alignment contact is evaluated. An electrical test of the wafer is performed utilizing the aligned probe card, and the historical offset correction is updated based on the orientation value.

Method of test probe alignment control

A method of inserting dummy patterns includes providing a window area comprising a main pattern. The main pattern includes first patterns of a first type of features, and second patterns of a second type of features. The first and the second types are different types. The method further includes globally inserting first dummy patterns throughout the window area, wherein the first dummy patterns are dummy patterns of the first type of features; enlarging the main pattern to generate an enlarged main pattern, wherein the enlarged main pattern occupies an enlarged region of the window area; removing the portion of the first dummy patterns in the enlarged region from the first dummy patterns to generate first inversed dummy patterns; and combining the first patterns in the main pattern with the first inversed dummy patterns to generate first mask patterns for the first type of features.

Reverse dummy insertion algorithm

An integrated circuit structure includes a semiconductor wafer; integrated circuit devices in the semiconductor wafer; and a plurality of test pads on a top surface of the semiconductor wafer and connected to the integrated circuit devices. Test pads are grouped in pairs, with the test pads in a same pair are interconnected.

Test pad design for reducing the effect of contact resistances

A testline structure made for integrated circuit tests is presented. The structure includes an array of testline pads formed in the scribe line area or integrated circuit die area on a semiconductor substrate, a plurality of test devices formed under the pads area, and a select circuit selectively connecting one of the test devices. The testline structure of this invention enables access to a large number of test devices through the same number of pads as on a conventional testline and can be employed to conduct parametric, reliability, and functional tests on the same. A source measurement unit (SMU) in a conventional integrated circuit tester is employed to sense and force predetermined test conditions on the test device terminals and conduct accurate Kelvin tests on the selected device. A method of using this testline structure is also presented.

High accuracy and universal on-chip switch matrix testline

A method and structure is disclosed to measure spacing and misalignment of features in semiconductor integrated circuits. Three equally spaced, parallel first level conductive lines are formed on a first insulating layer with staircase patterns projecting both out of and into the inner edges of the outer lines. A second insulating layer is deposited and step contact vias are opened through the second insulating layer over the steps of the staircase patterns. The inner edge of the step contact via coincides with the inner edge of the step. Contact pad vias are opened through the second insulating layer over the outer lines and the step contact vias and the contact pad vias are filled with conductive material. A second level conductive line is formed over the second insulating layer parallel to said first level conductive lines and above the central first level conductive line. Resistor ladder patterns are formed projecting from both edges of said second level conductive line, the rungs of said ladder patterns being of equal length and being composed of rung conductive sections with a resistor section interposed. A center conductor contact pad is formed electrically connected to the second level conductive line. A right conductor contact pad is formed over the right contact pad via and a left conductor contact pad is formed over the left contact pad via. The resistances between the center conductor pad and the right conductor pad and between the center conductor pad and left conductor pad are measured. From these resistances are inferred which rungs of the resistor ladder patterns make contact with step contact vias of the outer first level conductive lines. This infers bounds for the distances, SR and SL, from the right and left outer first level conductive lines to the second level conductive line. Spacing and misalignment are calculated from these distances.

Electrical overlay/spacing monitor method using a ladder resistor

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Hsinchu, Taiwan

Tseng Chin Lo