Myson Technology Inc.

Myson Century, Inc.

Tsen-Shau Yang

Yuan-Chih Chung

Chien-Kuo Wang

Chun-Ming Chou

Jia-Der Hsieh

Chin-Chieh Chao

Yi-Chuan Peng

Chung-Pin Yuan

Wei-Shang Chu

A touch key control and icon display apparatus includes a first substrate, a light-emitting element, a second substrate, and a body portion. The light-emitting element is disposed adjacent to the first substrate. The second substrate includes a circuit layer configured to sense a touch. The body portion is disposed between the first and second substrates and includes a reflective surface that defines a chamber. The chamber is formed through the body portion and configured to receive the light-emitting element. The circuit layer includes an icon disposed adjacent to an opening of the chamber. A portion of light, from the light-emitting element, incident on the circuit layer can pass through the circuit layer, and another portion of the light can be reflected by the circuit layer.

Touch key control and icon display apparatus

A transceiver includes a control module and a transceiving module. The control module is configured to generate a control signal in response to a signal from a micro-control unit. The transceiving module is integrated with the control module. The transceiving module is configured to, in response to the control signal, broadcast a first electrical signal to a bus and receive a second electrical signal from the bus.

Controller area network node transceiver

A single-ended high-voltage level shifter for a TFT-LCD gate driver comprises a high-voltage power supply and a low-voltage power supply, a low-voltage NMOS transistor, a high-voltage NMOS transistor, and a high-voltage PMOS transistor. An input signal is applied at the gate of the low-voltage NMOS transistor. The source of the low-voltage NMOS transistor is connected to the low-voltage power supply. The source of the high-voltage NMOS transistor is connected to the drain of the low-voltage NMOS transistor. The high-voltage NMOS transistor has a first reference voltage applied at its gate. The level of the first reference voltage is between the input-signal level and the high-voltage power supply. The drain of the high-voltage PMOS transistor is connected to the drain of the high-voltage NMOS transistor. The source of the high-voltage PMOS transistor is connected to the high-voltage power supply. The high-voltage PMOS transistor has a second reference voltage applied at its gate. The second reference voltage keeps the high-voltage PMOS transistor in ON-state and is at a level higher than the first reference voltage. The drain of the high-voltage PMOS transistor is employed as the output end connected to an output buffer of the next stage.

Single-ended high-voltage level shifter for a TFT-LCD gate driver

An analog-to-digital converter receives slow-varying analog voltages from a sensing device and converts the slow-varying analog voltages to digital signals. The sensing device generates a slow-varying analog voltage directly proportional to absolute temperature. The analog-to-digital converter includes a second counter which receives the pulse train from the second voltage controlled oscillator that counts the number of pulses which informs the first counter whenever the count value thereof reaches a fixed number and resets the count value thereof to zero. As the first counter is being informed by the second counter, its count value is read and then reset to zero. The read count represents a digital signal corresponding to the slow-varying analog voltages input.

CMOS analog-to-digital converter and temperature sensing device using

The object of the present invention is to provide a clock synthesizer IC which can produce clock signals with much lower radiated EMI. The clock synthesizer IC comprises: a forward programmable counter for dividing the frequency of input clock signals by M; a feedback programmable counter for dividing the frequency of input clock signals by N; a phase-frequency detector for accepting one input signal from said forward programmable counter and another from said feedback programmable counter, outputting two signals whose levels are determined by phase difference of said two input signals; a loop filter accepting the output signal of said phase-frequency detector and outputting a signal with high-frequency component filtered out; a voltage-controlled oscillator accepting the output signal of said loop filter and outputting a signal as the input signal of said feedback programmable counter and as the output signal of the whole clock synthesizer whose frequency is determined by input voltage; a programmable logic array, for controlling the dividing-number M and N of said forward programmable counter and said feedback programmable counter respectively. An up/down counter for controlling the dividing-number N of said feedback programmable counter in cooperation with said programmable logic array by way of dividing the binary representation of said dividing-number D.sub.n D.sub.(n-1) . . . D.sub.1 D.sub.0 into two groups: D.sub.n . . . D.sub.k and D.sub.(k-1) . . . D.sub.0 and controlling them by said programmable logic array and said up/down counter respectively in which the time interval of transition of D.sub.n D.sub.(n-1) . . . D.sub.1 D.sub.0 is determined by said up/down counter.

Clock synthesizer for low EMI applications

A driver circuit is to be used with an attachment unit interface in a network system and receives complementary data signals and an enable signal from constant current source and a differential transistor pair which includes a pair of differential transistors and a pair of load resistors. Each of the differential transistors has a gate terminal which receives one of the complementary data signals, a drain terminal which is connected to one of the load resistors, and a source terminal which is connected to the constant current source. A switch network is connected to the drain terminal of the differential transistors and is activated by the enable signal so as to generate a differential voltage output. Each of a pair of source followers has a gate terminal connected to the switch network and a source terminal The source followers receive the differential voltage output from the switch network. A switching transistor has a gate terminal which receives the enable signal, and source and drain terminals which are connected to the source terminal of a respective one of the source followers and which are further connected to a respective external pull-down load resistor. The source and drain terminals of the switching transistor are to be connected to the attachment unit interface.

Growing community of inventors

Taipei, Taiwan

Tsen-Shau Yang