Nan Ya Technology Corporation

Nanya Technology Corporatiion

Tse-Yao Huang

Yi-Nan Chen

Shing-Yih Shih

Hsien-Wen Liu

Yu-Chi Sun

Tzu-Ching Tsai

Hui-Min Mao

Chih-Ching Lin

Hsih-Yang Chiu

Ming-Cheng Chang

Kuo-Chien Wu

Chung-Peng Hao

Jin-Tau Huang

Chiang-Lin Shih

Jeng-Ping Lin

Yinan Chen

Mao-Ying Wang

Wen-Chieh Wang

Chao-Wen Lay

Chang Rong Wu

Hsiu-Chun Lee

Wei-Hui Hsu

Change-Rong Wu

Bing-Hung Chen

The present application discloses provides a method for fabricating a semiconductor device. The method includes forming a first insulating layer on a substrate; forming a bottom contact in the first insulating layer; sequentially forming a bottom dielectric layer, a lower middle dielectric layer, a higher middle dielectric layer, and a top dielectric layer on the first insulating layer; performing an opening-etching process to form an opening along the top dielectric layer, the higher middle dielectric layer, the lower middle dielectric layer, and the bottom dielectric layer to expose the bottom contact; and forming a conductive structure in the opening. A carbon concentration of the lower middle dielectric layer is greater than a carbon concentration of the bottom dielectric layer.

Method for fabricating semiconductor device with multi-carbon-concentration dielectrics

A semiconductor device includes an interconnect structure disposed over a semiconductor substrate. The interconnect structure includes a first interconnect portion and a second interconnect portion. The semiconductor device also includes a first porous dielectric portion disposed between the first interconnect portion and the second interconnect portion, and a dielectric layer surrounding the first porous dielectric portion. The semiconductor device further includes a bonding pad disposed over the dielectric layer and the first porous dielectric portion. The bonding pad and the first porous dielectric portion are separated by a first air gap.

Semiconductor device with air gap and method for preparing the same

The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; a bottom interconnector layer positioned in the substrate; a bottom dielectric layer positioned on the bottom glue layer; an interconnector structure positioned along the bottom dielectric layer and the bottom glue layer, positioned on the bottom interconnector layer, and positioned on the bottom dielectric layer; a top glue layer conformally positioned on the bottom dielectric layer and the interconnector structure; a top dielectric layer positioned surrounding the top glue layer. A top surface of the top glue layer and a top surface of the top dielectric layer are substantially coplanar. The top dielectric layer is porous.

Semiconductor device with porous layer and method for fabricating the same

A method for forming a memory device includes: forming an array of memory cells, wherein the memory cells respectively include an access transistor embedded in a semiconductor substrate and a storage capacitor over the semiconductor substrate and coupled to the access transistor; and forming a peripheral circuit around the memory cells, wherein the peripheral circuit includes a first transistor and a second transistor on the semiconductor substrate and each including a protruding channel structure and a gate structure covering the protruding channel structure, the protruding channel structure has a bottom part and an upper part, and the upper part of the protruding channel structure has a top width and a bottom width smaller than the top width.

Method for manufacturing memory device having a protruding channel structure

The present application discloses a semiconductor structure and a method for fabricating the semiconductor device. The semiconductor structure includes a substrate; a conductive feature positioned on the substrate; an anti-back sputtering layer positioned on the conductive feature; and a first hard mask structure positioned on the anti-back sputtering layer. The anti-back sputtering layer has etching selectivity to the first hard mask structure.

Semiconductor structure with anti-back-sputter layer

A semiconductor device structure includes a first lower semiconductor structure disposed over a semiconductor substrate. The first lower semiconductor structure has a first sidewall and a second sidewall opposite to the first sidewall. The semiconductor device structure also includes a first upper semiconductor structure covering a top surface and the first sidewall of the first lower semiconductor structure. The first lower semiconductor structure and the first upper semiconductor structure include different materials. The semiconductor device structure further includes a first oxide portion disposed over the semiconductor substrate and extending along the second sidewall of the first lower semiconductor structure. The first oxide portion has an L-shape.

Semiconductor device structure including composite interconnect

Composite interconnect semiconductor device structure

A semiconductor device structure includes a first dielectric layer disposed over a semiconductor substrate, and a second dielectric layer disposed over the first dielectric layer. The semiconductor device structure also includes a spacer structure disposed in the second dielectric layer, and a conductive structure penetrating through the second dielectric layer and extending into the first dielectric layer. The conductive structure is surrounded by the spacer structure. The semiconductor device structure further includes a liner layer separating the conductive structure from the first dielectric layer, the second dielectric layer and the spacer structure. The liner layer has a tapered sidewall in direct contact with the first dielectric layer.

Semiconductor device structure with liner layer having tapered sidewall and method for preparing the same

The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate including an array area and a peripheral area; and a peripheral gate structure including: a peripheral gate dielectric layer inwardly positioned in the peripheral area of the substrate and including a U-shaped cross-sectional profile; a peripheral gate conductor including a bottom portion positioned on the peripheral gate dielectric layer and a neck portion positioned on the bottom portion; and a peripheral gate capping layer positioned on the peripheral gate dielectric layer and the bottom portion, and surrounding the neck portion. A top surface of the peripheral gate capping layer and a top surface of the neck portion are substantially coplanar.

Semiconductor device with peripheral gate structure and method for fabricating the same

The present application discloses a semiconductor device with adjustment layers and a method for fabricating the semiconductor device with the adjustment layers. The semiconductor device includes a substrate, an interconnection structure positioned on the substrate, a contact positioned penetrating the interconnection structure, two adjustment layers positioned on sidewalls of the contact, a contact barrier layer positioned between the interconnection structure and the contact and between the substrate and the contact, wherein the two adjustment layers are positioned between the contact and the contact barrier layer. A bottom segment of the contact barrier layer is positioned between the substrate and the contact, and bottom most points of the two adjustment layers contact the bottom portion of the contact barrier layer.

Semiconductor device with adjustment layers and method for fabricating the same

The present application discloses a semiconductor device. The semiconductor device includes a substrate; a peripheral gate structure including: a peripheral gate insulating layer inwardly positioned in the substrate and including a U-shaped cross-sectional profile, a peripheral work function layer positioned on the peripheral gate insulating layer and including a recess, a first peripheral interconnect layer positioned on the peripheral work function layer, a first peripheral liner layer positioned between the peripheral work function layer and the first peripheral interconnect layer, and a peripheral capping layer positioned on the first peripheral interconnect layer. The peripheral work function layer includes titanium, titanium nitride, silicon, silicon germanium, or a combination thereof. The first peripheral liner layer includes graphene. The first peripheral interconnect layer includes tungsten, tungsten nitride, or a combination thereof.

Semiconductor device with work function layer

The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; a plurality of first conductive structures positioned on the substrate; a plurality of outer liner layer each positioned on a corresponding sidewall of the plurality of first conductive structures; and a plurality of bottom inter-feature dielectric layers positioned on the plurality of outer liner layers and between the plurality of first conductive structures. Each of the outer liner layers includes one or more species of vanadium oxide. The plurality of bottom inter-feature dielectric layers are porous.

Semiconductor device with porous dielectric layers and method for fabricating the same

The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; a word line structure positioned in the substrate; a plurality of impurity regions positioned in the substrate and adjacent to the word line structure; a plurality of bottom shallow contacts positioned on the word line structure; a first interconnect layer positioned on the plurality of bottom shallow contacts; a plurality of top shallow contacts positioned on the first interconnect layer; and a plurality of deep contacts positioned on the plurality of impurity regions. Top surfaces of the plurality of top shallow contacts and top surfaces of the plurality of deep contacts are substantially coplanar.

Semiconductor device with shallow contacts and method for fabricating the same

The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a first tier structure positioned on a substrate and including: a plurality of conductive features of the first tier structure positioned over the substrate, and a decoupling unit of the first tier structure positioned between the plurality of conductive features of the first tier structure, and including a bottle-shaped cross-sectional profile; a first set of solid alignment marks including: a first-tier-alignment mark of the first set of solid alignment marks positioned on the decoupling unit of the first tier structure; a first set of spaced alignment marks including: a first-tier-alignment mark of the first set of spaced alignment marks positioned in a mirror manner of the first-tier-alignment mark of the first set of solid alignment marks according to a first axis of symmetry.

Semiconductor device with an insulative decoupling unit positioned between two of a plurality of conductive features

The present application discloses a contact structure, a semiconductor device, and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; an impurity region positioned in the substrate; an intervening conductive layer positioned on the impurity region; a bottom conductive layer positioned on the bottom conductive layer; a conductive capping layer positioned on the bottom conductive layer; a top conductive layer positioned on the conductive capping layer. The intervening conductive layer, the bottom conductive layer, the conductive capping layer, and the top conductive layer configure a contact structure. The bottom conductive layer includes germanium or silicon germanium. The bottom conductive layer includes n-type dopants or p-type dopants.

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Taipei, Taiwan

Tse-Yao Huang