Mediatek Corporation

Tse-Hsien Yeh

Shih-Che Hung

Chien-Kai Kao

Yi-Hsien Cho

Chen-Yu Hsiao

Li-Hung Chiueh

The present invention includes a CDR circuit including a phase detector, a neural network circuit, a controller and a clock signal generator is disclosed. The phase detector is configured to use a clock signal to sample an input signal to generate a plurality of phase detection results. The neural network circuit is coupled to the phase detector, and is configured to receive the plurality of phase detection results to determine information of a frequency difference between the clock signal and the input signal. The controller is configured to generate a control signal according to the information of the frequency difference between the clock signal and the input signal. The clock signal generator is configured to use the control signal to adjust a phase or frequency of the clock signal outputted to the phase detector.

Clock and data recovery circuit using neural network circuit to obtain frequency difference information

The present invention provides a CDR circuit including a first phase detector, a controller and a phase filter. In the operations of the CDR, the first phase detector is configured to compare a phase of an input signal and a phase of a clock signal to generate a first phase detection result. The controller is configured to generate a control signal according to the first phase detection result. The phase filter is configured to receive the control signal and an auxiliary signal to generate the clock signal, wherein the auxiliary signal is generated according to the first phase detection result.

Clock and data recovery and associated signal processing method

The present invention provides a receiver, wherein the receiver includes a plurality of receiving circuit and a skew detection and alignment circuit. The receiving circuit is arranged for receiving a plurality of input signals from a plurality of channels, wherein each of the receiving circuits receives at least one of the input signals to generate an output signal. The skew detection and alignment circuit is arranged for determining skew information according to at least one of the input signals and the output signals, wherein the skew information is used to control delay amounts corresponding to the input signals or the output signals.

Channel skew calibration method and associated receiver and system

A clock data recovery apparatus includes an oscillator, a sampler circuit, and a frequency control circuit. The oscillator generates a clock signal according to a bias voltage. The sampler circuit samples an input data signal to generate a sampling signal according to the clock signal. The frequency control circuit generates the bias voltage by performing integration calculation, digital-to-analog conversion, and low-pass filtering for the sampling signal.

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Taipei, Taiwan

Tse-Hsien Yeh