Nan Ya Technology Corporation

Tsang-Po Yang

Jui-Hsiu Jao

Chun-Shun Huang

Hsueh-Han Lu

Yu-Ting Lin

Shian-Jyh Lin

Chiang-Lin Shih

Yu-Che Li

The present disclosure provides a semiconductor structure having a test structure. The semiconductor structure includes a wafer and a test structure disposed on the wafer. The test structure includes a first device having a first source/drain layer and a first gate layer disposed above the first source/drain layer; a second device, having a second source/drain layer and a second gate layer disposed above the second source/drain layer, the second gate layer connected to the first gate layer; a third device, disposed adjacent to the first device and having a third source/drain layer. The first gate layer is disposed above the third source/drain layer, and the first gate layer is disposed along a first direction and the second gate layer is disposed along a second direction orthogonal to the first direction.

Semiconductor structure

The present disclosure provides a semiconductor structure having a test structure. The semiconductor structure includes a semiconductor substrate, a memory device and a test structure. The memory device is disposed on the semiconductor substrate, and includes a device area and an edge area. The edge area surrounds the device area. The test structure is disposed on the semiconductor substrate, and includes a dummy area, a test edge area and a plurality of unit cells. The test edge area surrounds the dummy area. The plurality of unit cells are disposed in the test edge area, and the dummy area is free of the unit cells. A dimension of the test edge area in a top view is different from a dimension of the edge area in the top view.

Semiconductor structure with test structure

A semiconductor structure and a method of manufacturing a semiconductor structure are provided. The method includes forming a conductive layer on a precursor memory structure, in which the precursor memory structure includes a plurality of transistors and a plurality of contact plugs disposed on and connected to the transistors. The conductive layer in a TEG region is then patterned to form a first patterned conductive layer on the precursor memory structure. The first patterned conductive layer is then patterned to form a plurality of first landing pads extending along a first direction, in which the first landing pads are separated from each other in a second direction that is different from the first direction and are electrically connected to each other through the contact plugs and the transistors.

Semiconductor structure and method of manufacturing the same

The present disclosure provides a semiconductor structure having a test structure. The semiconductor structure includes a semiconductor substrate, a memory device and a test structure. The memory device is disposed on the semiconductor substrate, and includes a device area and an edge area. The edge area surrounds the device area. The test structure is disposed on the semiconductor substrate, and includes a dummy area, a test edge area and a plurality of unit cells. The test edge area surrounds the dummy area. The unit cells have a first group disposed in the dummy area and a second group disposed in the test edge area. The second group of unit cells includes the outermost unit cells of the plurality of unit cells. A shape surrounded by the edge area in a top view is different from a shape surrounded by the test edge area in the top view.

The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a first testing area, a word line structure positioned in the first testing area and arranged parallel to a first axis, a first column of capacitor contact structures positioned in the first testing area and arranged parallel to a second axis perpendicular to the first axis, a second column of capacitor contact structures positioned adjacent to the first column of capacitor contact structures and arranged parallel to the first column of capacitor contact structures, and a first testing structure including a first drain portion extended along the second axis and a first source portion extended along the second axis. The first drain portion is positioned on the first column of capacitor contact structures and the first source portion is positioned on the second column of capacitor contact structures.

Semiconductor device with testing structure and method for fabricating the same

The semiconductor structure includes a substrate, a deep well, a first doped region, a source/drain region, and a first heavily doped region. The substrate has a first conductivity type. The deep well has a second conductivity type disposed on the substrate. The first doped region has the first conductivity type disposed on the deep well. The source/drain region has the second conductivity type disposed on the first doped region. The first heavily doped region has the second conductivity type disposed in a first top region of the source/drain region, in which the first conductivity type is opposite to the second conductivity type.

The present disclosure provides a semiconductor structure having a test structure. The semiconductor structure includes a wafer and a test structure. The test structure is disposed on the wafer, and includes a first device and a second device. The first device includes a first source/drain layer and a first gate layer disposed above the first source/drain layer. The second device includes a second source/drain layer and a second gate layer disposed above the second source/drain layer. The second gate layer is connected to the first gate layer. The first gate layer is disposed along a first direction and the second gate layer is disposed along a second direction orthogonal to the first direction.

A test array structure includes a substrate, first and second cells, first and second bit-line rings and four word-lines. Each of the first and second cells has a first drain region, a first gate region, a source region, a second gate region and a second drain region connected together in sequence. The first drain region and the first gate region of the first cell are located within the first bit-line ring. The second drain region and the second gate region of the first cell are located between the first and second bit-line rings. The first drain region and the first gate region of the second cell is located within the second bit-line ring. The second drain region of the first cell and the first drain region of the second cell are located between the two immediately-adjacent word-lines.

Test array structure, wafer structure and wafer testing method

A method includes forming a transistor over a substrate; forming a conductive structure over the substrate, such that a first end of the conductive structure is electrically coupled to a gate of the transistor, and a second end of the conductive structure is electrically coupled to the substrate; applying biases to the gate of the transistor and source/drain structures of the transistor; determining whether the first end and the second end of the conductive structure are electrically connected; generating, based on the determination, a first result indicating that the first end and the second end of the conductive structure are electrically connected; and qualifiying the conductive structure as an antenna in response to the first result.

Semiconductor structure and manufacturing method thereof

A method includes forming a transistor over a substrate; forming a conductive structure over the substrate, such that a first end of the conductive structure is electrically coupled to a gate of the transistor, and a second end of the conductive structure is electrically coupled to the substrate; applying biases to the gate of the transistor and source/drain structures of the transistor; determining whether the first end and the second end of the conductive structure are electrically connected; generating, based on the determination, a first result indicating that the first end and the second end of the conductive structure are electrically connected; and qualifying the conductive structure as an antenna in response to the first result.

A semiconductor structure includes a first anti-fuse structure, a second anti-fuse structure and a first metal layer. The second anti-fuse structure is disposed over the first anti-fuse structure. The first metal layer is between the first anti-fuse structure and the second anti-fuse structure. A first contact is disposed between the first anti-fuse structure and the first metal layer to connect thereof. A second contact is disposed between the second anti-fuse structure and the first metal layer to connect thereof.

Growing community of inventors

Taipei, Taiwan

Tsang-Po Yang