Taiwan Semiconductor Manufacturing Comp. Ltd.

National Science Council

Tsang-Jiuh Wu

Wen-Chih Chiou

Chen-Hua Douglas Yu

Yung-Chi Lin

Ku-Feng Yang

Hsin-Yu Chen

Lin-Chih Huang

Ming-Tsu Chung

Ebin Liao

Hong-Ye Shih

Hung-Pin Chang

Tasi-Jung Wu

Shin-Puu Jeng

Hsiao Yun Lo

An-Jhih Su

Li-Hsien Huang

Cheng-Hung Chang

Chia-Lin Yu

Yuan-Hung Liu

Chun Hua Chang

Hsiang-Yi Wang

Chia-Yin Chen

Darryl Kuo

Der-Chyang Yeh

Chi-Hsi Wu

Ming Shih Yeh

Jiung Wu

HsiaoYun Lo

Li-Te S Lin

Chen-Yu Tsai

Li-Chih Chao

Ping-Jung Wu

Jing-Cheng Lin

Syun-Ming Jang Jang

Yi-Hsiu Chen

Yu-Kuang Liao

Yang-Chih Hsueh

Chien-Ming Chiu

Kuan-Liang Lai

Jia-Xsing Li

Shau-Lin Shue

Cheng-Chieh Hsieh

Hung-An Teng

Yen-Hung Chen

Pei-Ching Kuo

Yin-Hua Chen

Chao-Cheng Chen

Hun-Jan Tao

Chia-Hao Hsu

Hua-Tai Lin

Ming-Chung Liang

Chen-Nan Yeh

Ken-Yu Chang

Jian-Hong Chen

Hsin-Yi Tsai

Yu-Jen Cheng

Chien Rhone Wang

Chih-Wei Lai

Hui-Chang Yu

Tzu-Cheng Lin

Yan-Zuo Tsai

Chwung-Shan Kou

Bang-Chien Ho

Ching-Hui Ma

Tung-Hsien Wu

Shyue-Sheng Lu

I-Chun Hsu

Hao-Wen Ko

In an embodiment, a device includes: a first wafer including a first substrate and a first interconnect structure, a sidewall of the first interconnect structure forming an obtuse angle with a sidewall of the first substrate; and a second wafer bonded to the first wafer, the second wafer including a second substrate and a second interconnect structure, the sidewall of the first substrate being laterally offset from a sidewall of the second substrate and a sidewall of the second interconnect structure.

Wafer bonding method

A semiconductor device includes a through-substrate via extending from a frontside to a backside of a semiconductor substrate. The through-substrate via includes a concave or a convex portion adjacent to the backside of the semiconductor substrate. An isolation film is formed on the backside of the semiconductor substrate. A conductive layer includes a first portion formed on the concave or convex portion of the through substrate via and a second portion formed on the isolation film. A passivation layer partially covers the conductive layer.

Semiconductor device having backside interconnect structure on through substrate via

A semiconductor device includes a photonic die and an optical die. The photonic die includes a grating coupler and an optical device. The optical device is connected to the grating coupler to receive radiation of predetermined wavelength incident on the grating coupler. The optical die is disposed over the photonic die and includes a substrate with optical nanostructures. Positions and shapes of the optical nanostructures are such to perform an optical transformation on the incident radiation of predetermined wavelength when the incident radiation passes through an area of the substrate where the optical nanostructures are located. The optical nanostructures overlie the grating coupler so that the incident radiation of predetermined wavelength crosses the optical die where the optical nanostructures are located before reaching the grating coupler.

Semiconductor device and manufacturing method thereof having grating coupled dies and nanostructures

A semiconductor structure including a first die, a second die stacked on the first die, a smoothing layer disposed on the first die and a filling material layer disposed on the smoothing layer. The second die has a dielectric portion and a semiconductor material portion disposed on the dielectric portion. The smoothing layer includes a first dielectric layer and a second dielectric layer, and the second dielectric layer is disposed on the first dielectric layer. The dielectric portion is surrounded by the smoothing layer, and the semiconductor material portion is surrounded by the filling material layer. A material of the first dielectric layer is different from a material of the second dielectric layer and a material of the filling material layer.

Semiconductor structure and manufacturing method thereof

A method includes bonding a top die to a bottom die, depositing a first dielectric liner on the top die, and depositing a gap-fill layer on the first dielectric liner. The gap-fill layer has a first thermal conductivity value higher than a second thermal conductivity value of silicon oxide. The method further includes etching the gap-fill layer and the first dielectric liner to form a through-opening, wherein a metal pad in the bottom die is exposed to the through-opening, depositing a second dielectric liner lining the through-opening, filling the through-opening with a conductive material to form a through-via connecting to the metal pad, and forming a redistribution structure over and electrically connecting to the top die and the through-via.

3DIC with gap-fill structures and the method of manufacturing the same

A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes an interconnect structure disposed over a semiconductor substrate, contact pads disposed on the interconnect structure, a dielectric structure disposed on the interconnect structure and covering the contact pads, bonding connectors covered by the dielectric structure and landing on the contact pads, and a dummy feature covered by the dielectric structure and laterally interposed between adjacent two of the bonding connectors. Top surfaces of the bonding connectors are substantially coplanar with a top surface of the dielectric structure, and the bonding connectors are electrically coupled to the interconnect structure through the contact pads.

Semiconductor structure comprising dummy feature interposed between the bonding connectors

Methods of singulation and bonding, as well as structures formed thereby, are disclosed. A method includes singulating a first chip and after the singulating the first chip, bonding the first chip to a second chip. The first chip includes a first semiconductor substrate and a first interconnect structure on a front side of the first semiconductor substrate. The singulating the first chip includes etching through a back side of the first semiconductor substrate through the first interconnect structure.

Singulation and bonding methods and structures formed thereby

A manufacturing method of a through substrate via includes at least the following steps. A protective liner is formed within an opening of a dielectric layer, where the opening exposes a portion of a semiconductor substrate underlying the dielectric layer. The portion of the semiconductor substrate is removed through the opening, where an overhang portion is formed at a top edge of the semiconductor substrate and masked by the protective liner after the removing. The overhang portion of the semiconductor substrate, the protective liner, and a portion of the dielectric layer adjoining the protective liner is removed to form a via hole. A conductive material is formed in the via hole.

Embodiments provide a high aspect ratio via for coupling a top electrode of a vertically oriented component to the substrate, where the top electrode of the component is coupled to the via by a conductive bridge, and where the bottom electrode of the component is coupled to substrate. Some embodiments provide for mounting the component by a component wafer and separating the components while mounted to the substrate. Some embodiments provide for mounting individual components to the substrate.

Via for component electrode connection

A method includes forming a plurality of dielectric layers over a semiconductor substrate, etching the plurality of dielectric layers and the semiconductor substrate to form an opening, depositing a first liner extending into the opening, and depositing a second liner over the first liner. The second liner extends into the opening. The method further includes filling a conductive material into the opening to form a through-via, and forming conductive features on opposing sides of the semiconductor substrate. The conductive features are electrically interconnected through the through-via.

TSV structure and method forming same

A method for forming a via in a semiconductor device and a semiconductor device including the via are disclosed. In an embodiment, the method may include bonding a first terminal and a second terminal of a first substrate to a third terminal and a fourth terminal of a second substrate; separating the first substrate to form a first component device and a second component device; forming a gap fill material over the first component device, the second component device, and the second substrate; forming a conductive via extending from a top surface of the gap fill material to a fifth terminal of the second substrate; and forming a top terminal over a top surface of the first component device, the top terminal connecting the first component device to the fifth terminal of the second substrate through the conductive via.

Via for semiconductor device connection and methods of forming the same

Provided are a semiconductor device and a method for manufacturing the same, and a semiconductor package. The semiconductor device includes a die stack and a cap substrate. The die stack includes a first die, second dies stacked on the first die, and a third die stacked on the second dies. The first die includes first through semiconductor vias. Each of the second dies include second through semiconductor vias. The third die includes third through semiconductor vias. The cap substrate is disposed on the third die of the die stack. A sum of a thickness of the third die and a thickness of the cap substrate ranges from about 50 μm to about 80 μm.

Semiconductor device and method for manufacturing the same, and semiconductor package

A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes a semiconductor substrate, an interconnection structure, through substrate vias, conductive pillars and dummy conductive pillars. The interconnection structure is disposed at a front side of the semiconductor substrate, and comprises a stack of dielectric layers and interconnection elements spreading in the stack of dielectric layers. The through substrate vias separately penetrate through the semiconductor substrate and the stack of dielectric layers. The conductive pillars are disposed at a front side of the interconnection structure facing away from the semiconductor substrate, and respectively in electrical connection with one of the through substrate vias. The dummy conductive pillars are disposed aside the conductive pillars at the front side of the interconnection structure.

Semiconductor structure with through substrate vias and manufacturing method thereof

Method of forming semiconductor device having backside interconnect structure on through substrate via

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Hsinchu, Taiwan

Tsang-Jiuh Wu