Nan Ya Technology Corporation

Tsai-Yu Huang

Sheng-Chuan Su

Raymond Wang

A three-dimensional integrated circuit is disclosed, including a first interposer including through substrate vias (TSV) therein and circuits thereon; a plurality of first active dies disposed on a first side of the first interposer, a plurality of first intermediate interposers, each including through substrate vias (TSV), disposed on the first side of the first interposer, and a second interposer including through substrate vias (TSV) therein and circuits thereon supported by the first intermediate interposers.

Three-dimensional integrated circuits and fabrication thereof

A split gate flash memory. A drain is disposed in the bottom of a trench formed in a substrate. A source is disposed in the substrate outside the trench. A striped floating gate is disposed at a sidewall of the trench, wherein one side of the striped floating gate is near the bottom of the trench, and the other side of the striped floating gate protrudes above the substrate. A control gate winds along the floating gate, wherein one side of the control gate is near the bottom of the trench, and the other side of the control gate in outside the trench. A metal bit line connects to the drain.

Split gate flash memory and formation method thereof

A method of etching a mask layer as a protecting layer for metal contact windows uses a victim layer with slopes to avoid undercutting. First, a mask layer is formed on a semiconductor substrate. Next, a photoresist with patterns is formed on the surface of the mask layer. Next, a victim layer is formed on the surface of the photoresist according to the photoresist topography, such that a plurality of slopes is formed on the sidewalls of the photoresist. The photoresist and the victim layer with slopes are used as the etching mask to etch the mask layer to form patterns.

Growing community of inventors

Hsinchu Hsien, Taiwan

Tsai-Yu Huang