Taiwan Semiconductor Manufacturing Comp. Ltd.

Industrial Technology Research Institute

Tsai-Sheng Gau

Ru-Gun Liu

Shih-Ming Chang

Chih-Ming Lai

Ming-Feng Shieh

Chun-Kuang Chen

Wen-Chun Huang

Ken-Hsien Hsieh

Shau-Lin Shue

Chung-Ju Lee

Burn Jeng Lin

Chih-Ming Ke

Ming-Hui Chih

Tien-I Bao

Yung-Sung Yen

Kuei-Shun Chen

Chin-Hsiang Lin

Yung-Hsu Wu

Te-Chih Huang

Chia-Ping Chiang

Li-Jui Chen

Tsong-Hua Ou

Ta-Ching Yu

Chia-Tien Wu

Wei-Liang Lin

Cheng-Hsiung Tsai

Chih-Wei Hsu

Chi-Cheng Hung

Hua-Tai Lin

Ya-Ting Chang

Burn-Jeng Lin

Wen-Li Cheng

Ching-Yu Chang

Shinn-Sheng Yu

Ying-Chou Cheng

Ping-Chieh Wu

Jen-Chieh Shih

Jyu-Horng Shieh

Chia-Ying Lee

Kuei Shun Chen

Jaw-Jung Shin

Yao-Ching Ku

Chin-Yuan Tseng

Yu-Po Tang

Hai-Ching Chen

Tzung-Chi Fu

Hsiang-Huan Lee

Cheng-Cheng Kuo

Chih-Yang Yeh

Fu-Jye Liang

Yu-Sheng Chang

Boren Luo

Wen-Hao Liu

Chung-Te Lin

Hsin-Chang Lee

Anthony Yen

Jeng-Horng Chen

Shy-Jay Lin

Hung-Chang Hsieh

Sheng-Liang Pan

Wen-Ju Preet Yang

De-Fang Chen

Chun-Yu Lin

Chien-Wei Wang

Gwan Sin Chang

Yen-Chun Huang

Kai-Hsiung Chen

Kuei-Liang Lu

Chang-Ming Dai

George Liu

Chang-Cheng Hung

Nian-Fuh Cheng

Ruei-Hung Jang

Kuan-Hsin Lo

Pi-Tsung Chen

Yi-Jie Chen

Wen-Hung Tseng

Horng-Huei Tseng

Li-Chun Tien

Ziwei Fang

Heng-Hsin Liu

Dian-Hau Chen

Huan-Just Lin

Ta-Cheng Lien

Pei-Cheng Hsu

Wen-Chuan Wang

Chia-Hui Lin

Chii-Ping Chen

Chia-Chu Liu

Yen-Liang Chen

Heng-Jen Lee

Hsu-Ting Huang

Joy Cheng

Shuo-Yen Chou

Ko-Bin Kao

Dong-Hsu Cheng

Meng-Wei Chen

Chin-Chiu Hsia

Hsin Chang

Hsiao-Tzu Lu

The present disclosure provides a method of patterning a target material layer over a semiconductor substrate. The method includes steps of forming a spacer feature over the target material layer using a first sub-layout and performing a photolithographic patterning process using a second sub-layout to form a first feature. A portion of the first feature extends over the spacer feature. The method further includes steps of removing the portion of the first feature extending over the spacer feature and removing the spacer feature. Other methods and associated patterned semiconductor wafers are also provided herein.

Methods for integrated circuit design and fabrication

A method includes forming a material layer over a substrate, forming a first hard mask (HM) layer over the material layer, forming a first trench, along a first direction, in the first HM layer. The method also includes forming first spacers along sidewalls of the first trench, forming a second trench in the first HM layer parallel to the first trench, by using the first spacers to guard the first trench. The method also includes etching the material layer through the first trench and the second trench, removing the first HM layer and the first spacers, forming a second HM layer over the material layer, forming a third trench in the second HM layer. The third trench extends along a second direction that is perpendicular to the first direction and overlaps with the first trench. The method also includes etching the material layer through the third trench.

Method of fabricating semiconductor device with reduced trench distortions

Implementations of the present disclosure provide coloring methods that sort and pre-color nodes of G0-linked networks in a multiple-patterning technology (MPT)-compliant layout design by coordinate. In one embodiment, a method includes identifying target networks in a circuit layout, each target network having two or more linked nodes representing circuit patterns, and each target network being presented in an imaginary X-Y coordinate plane, assigning a first feature to a first node in each target network, the first node is determined using a coordinate-based method, and assigning the first feature and a second feature to remaining nodes in each target network in an alternating manner so that any two immediately adjacent linked nodes in each target network have different features.

Method for coloring circuit layout and system for performing the same

A method for preparing a pellicle assembly includes reducing the thickness of one or more initial membrane(s) to obtain a pellicle membrane. The pellicle membrane is then affixed to a mounting frame to obtain the pellicle assembly. Compressive pressure can be applied to reduce the thickness of the initial membrane(s). Alternatively, the thickness can be reduced by stretching the initial membrane(s) to obtain an extended membrane. A mounting frame is then affixed to a portion of the extended membrane. The mounting frame and the portion of the extended membrane are then separated from the remainder of the extended membrane to obtain the pellicle assembly. The resulting pellicle assemblies include a pellicle membrane that is attached to a mounting frame. The pellicle membrane can be formed from nanotubes and has a combination of high transmittance, low deflection, and small pore size.

Pellicle assembly and method of making same

An integrated circuit structure includes a first metal feature formed into a first dielectric layer, a second metal feature formed into a second dielectric layer, the second dielectric layer being disposed on said first dielectric layer, and a via connecting the first metal feature to the second metal feature, wherein a top portion of the via is offset from a bottom portion of the via.

Via connection to a partially filled trench

A method includes forming a first layer on a substrate; forming a first plurality of trenches in the first layer by a patterning process; and forming a second plurality of trenches in the first layer by another patterning process, resulting in combined trench patterns in the first layer. A first trench of the second plurality connects two trenches of the first plurality. The method further includes forming dielectric spacer features on sidewalls of the combined trench patterns. A space between two opposing sidewalls of the first trench is completely filled by the dielectric spacer features and another space between two opposing sidewalls of one of the two trenches is partially filled by the dielectric spacer features.

Spacer etching process for integrated circuit design

The present disclosure provides a method for forming patterns in a semiconductor device. The method includes providing a substrate and a patterning-target layer over the substrate; patterning the patterning-target layer to form a main pattern; forming a middle layer over the patterning-target layer and a hard mask layer over the middle layer; patterning the hard mask layer to form a first cut pattern; patterning the hard mask layer to form a second cut pattern, a combined cut pattern being formed in the hard mask layer as a union of the first cut pattern and the second cut pattern; transferring the combined cut pattern to the middle layer; etching the patterning-target layer using the middle layer as an etching mask to form a final pattern in the patterning-target layer. In some embodiments, the final pattern includes the main pattern subtracting an intersection portion between main pattern and the combined cut pattern.

Mechanisms for forming patterns using multiple lithography processes

Growing community of inventors

Hsinchu, Taiwan

Tsai-Sheng Gau