Via Technologies, Inc.

Shanghai Zhaoxin Semiconductor Co., Ltd.

Via Alliance Semiconductor Co., Ltd.

Via Technologyies, Inc.

Tsai-Sheng Chen

Nai-Shung Chang

Yun-Han Chen

Shu-Hui Chen

Chang-Li Tan

Hsiu-Wen Ho

Chun-Yen Kang

Hsin-Kuan Wu

Chia-Hsing Yu

Sheng-Bang Ou Yang

A contact arrangement includes a plurality of contact groups. At least one of the contact groups includes a plurality of shared contacts, a plurality of dedicated contacts, and a plurality of ground contacts. The shared contacts in a first mode or a second mode transmit signals corresponding to the first mode or the second mode. The dedicated contacts transmit the signals corresponding to the first mode and do not transmit the signals corresponding to the second mode. The ground contacts surround the shared contacts and the dedicated contacts.

Contact arrangement and electronic assembly

A contact arrangement, including multiple contacts, is provided. The contacts are staggered. Some of the contacts form at least one contact group. The at least one contact group includes a pair of first contacts and eight second contacts. The pair of first contacts is a pair of differential signal contacts. The second contacts are arranged around the pair of first contacts. Two of the second contacts are arranged along a straight line perpendicular to a connecting line of the pair of first contacts. The position distribution and electrical properties of the other six of the second contacts are symmetrical to each other relative to the straight line.

Contact arrangement, circuit board, and electronic assembly

A contact arrangement, including multiple contacts, is provided. The contacts are staggered. Some of the contacts form at least one contact group. The at least one contact group includes a first contact and six second contacts. The second contacts are arranged around the first contact. When the first contact is a power contact or a ground contact, the second contacts are signal contacts. When the first contact is a signal contact, three of the second contacts are power contacts or ground contacts and are not adjacent to each other.

A circuit substrate and a semiconductor package structure are provided. The circuit substrate includes a body and a via hole array. The via hole array includes via hole column units periodically arranged along a first direction. Each via hole column unit includes first to sixth via holes passing through the body and electrically connected to a capacitor. Any two adjacent via holes of the first to sixth via holes transmit power and ground signals. The sixth via hole of one of the via hole column units is adjacent to the first via hole of another one of the via hole column units, which is adjacent to the one of the via hole column units. The sixth via hole of one of the via hole column units and the first via hole of another one of the via hole column units transmit power and ground signals.

Printed circuit board and semiconductor package structure

A circuit board including a first patterned conductive layer and a second patterned conductive layer isolated from the first patterned conductive layer is provided. The first patterned conductive layer has first signal traces and first ground traces. The second patterned conductive layer has second signal traces and second ground traces. An orthogonal projection of the second ground trace on the first patterned conductive layer partially overlaps at least one of the first signal traces. An orthogonal projection of the first ground trace on the second patterned conductive layer partially overlaps at least one of the second signal traces. An electronic assembly including the afore-described circuit board and a chip package connected thereto is also provided.

Circuit board and electronic assembly

A suspend-to-RAM controlling circuit includes a RAM (random access memory) controller, a logic circuit and at least one RAM module. The RAM controller has a controlling pin connected to the logic circuit. Each of the RAM modules has a first enable pin and a second enable pin connected to output pins of the logic circuit. The RAM module is driven to the STR (suspend-to-RAM) state after receiving an STR signal from the logic circuit. Therefore, the RAM controller can provide STR signals to a plurality of RAM modules by only one controlling pin in incorporation with the logic circuit.

Suspend-to-RAM controlling circuit

This invention relates to a layout structure for providing stable power supply to a four-layer motherboard and a main bridge chip substrate. In the invention, on the top signal layer and power path of the bottom solder layer for layout of the main bridge chip and on the power ring, the decoupling capacitors are connected in between the ground bonding pads/solder balls and the power bonding pads/solder balls of the power paths and power rings, so as to provide a stable power supply for the operation of the main bridge chip. In this invention, the ground bonding pad/solder ball connected with each power bonding pad/solder ball can be the closest ground bonding pad/solder ball to the power bonding pad/solder ball. In addition, in the embodiment of the main bridge chip substrate, decoupling capacitors can be disposed at four corners of the power ring or underneath the bonding wires, or can be packaged inside the molding compound.

Layout structure for providing stable power source to a main bridge chip substrate and a motherboard

A layout structure of a central processing unit (CPU) that supports two different package techniques, comprising a motherboard that comprises the layout structure and a layout method. The layout structure of the preferred embodiment according to the present invention from up to down sequentially places a top signal layer, a grounded layer, a power layer having a grounded potential, and a bottom solder layer in the area where the signals of the CPU are coupled to the signals of the control chip, so that the signals that are placed on the bottom solder layer can refer to a grounded potential area of the power layer. Therefore, part of signals of the CPU that are coupled to the control chip can be placed on the bottom solder layer. Since the preferred embodiment of the present invention provides more flexibility in the placement design, a layout structure that supports the Pentium IV CPUs of different package techniques can be designed on the motherboard of the 4 layers stack structure, and these two CPUs can be supported by the same control chip.

Layout structure and method for supporting two different package techniques of CPU

A chipset to support multiple CPU's and a layout method thereof. Those independent signal lines for delivering high frequency clock signals of the chipset are isolated from using by other signals without being multiplexed. Trace length of the independent signal line is shorter than that of the others. The spaces between the independent signal line and others are also larger than that between other signal lines. Signal transmission quality is significantly upgraded because the high frequency clock signal is not multiplexed and isolated from others.

Chipset supporting multiple CPU's and layout method thereof

A layout structure of a central processing unit (CPU) that supports two different package techniques, having a motherboard that comprising the layout structure and a layout method. The layout structure of the preferred embodiment according to the present invention from up to down sequentially placed a top signal layer, a grounded layer, a power layer having an operating potential area and a grounded potential area, and a bottom solder layer in the area where the signals of the CPU are coupled to the signals of the control chip, so that the signals that are placed on the bottom solder layer can refer to a grounded potential area of the power layer.

A memory control system for controlling write-enable signals. The memory control system has a first memory slot having a write-enable pin thereon, a second memory slot having a first write-enable pin and a second write-enable pin thereon and a control chipset having a write-enable pin and a dual-purpose write-enable/memory-parity-data pin thereon. The write-enable pin of the control chipset is connected to the write-enable pin of the first memory slot and the first write-enable pin of the second memory slot. The write-enable/memory-parity-data pin of the control chipset is connected to the second write-enable pin of the second memory slot. In this invention, since the design of the write-enable system is more flexible, length of trace line on a computer board can be greatly reduced. In addition, the system permits the incorporation of one cycle (1T) timing into design of memory access commands.

Memory control system for controlling write-enable signals

The present invention provides a computer motherboard having an Intel P54C compatible processor socket and a control chip having specifically arranged data pins and address pins which allows a short signal path arrangement from the processor socket to a cache tap RAM and a cache data RAM. The computer motherboard comprises a four-layer printed circuit board, a processor socket, a cache data RAM, a cache tag RAM, and a control chip. All these components are connected by using a high-order-bit data bus, a low-order-bit data bus, and an address bus through the top and bottom layers of the circuit board. The cache data RAM is positioned on the right side of the processor socket. The control chip is positioned on the top side of the cache data RAM and on the top-right side of the processor socket. It comprises an address section positioned at a bottom-middle portion of the control chip, a high-order-bit data section positioned at a bottom-right corner of the control chip, and a low-order-bit data section positioned at a bottom-left corner of the control chip. The cache tag RAM is positioned between the processor socket and the cache data RAM.

Growing community of inventors

Taipei, Taiwan

Tsai-Sheng Chen