Taiwan Semiconductor Manufacturing Comp. Ltd.

Global Unichip Corporation

Tsai-Ming Yang

Yen-Chung Chen

Yen-Chung Tony Chen

Ting-Hsu Chien

Yi-Lin Lee

Igor Elkanovich

Amnon Parnass

Chia-Hsiang Chang

Jen-Tai Hsu

Ting-Hao Wang

Pei Yu

Jia-Liang Chen

Cheng-Hung Wu

Po-Shing Yu

Yuan-Hung Lin

Chung-Kai Wang

Li-Hua Lin

Yu-Ju Chang

Ting-Chin Cho

Chao-Ching Huang

Li-Ya Tseng

Wei-An Liang

Yen-Wei Chen

Zanyu Yang

Chun-Hsu Chen

Shan-Jie Wang

An interface of integrated circuit (IC) die includes a plurality of the contact elements formed as a contact element pattern corresponding to a parallel bus. The contact elements are arranged in an array of rows and columns and divided into a transmitting group and a receiving group. The contact elements of the transmitting group have a first contact element sequence and the contact elements of the receiving group have a second contact element sequence, the first contact element sequence is identical to the second contact element sequence. The contact elements with the first contact element sequence and the second contact element sequence are matched when the contact element pattern is geometrically rotated by 180&#xb0; with respect to a row direction and a column direction.

Interface of integrated circuit die and method for arranging interface thereof

A circuit of communication interface between dies is provided. The circuit includes a first interface of the first die having a serializer to serialize an input data of N bits a serialized data for transmitting out and a second interface of the second die having a de-serializer to receive and deserialize the serialized data into a de-serialized data. In addition, an interconnection structure connected between the first die and the second die to connect the serializer and the de-serializer, wherein the interconnection structure is an interposer or a redistribution layer of a semiconductor structure to form a parallel bus for transmitting the serialized data in one line of the parallel bus between the first die and the second die. A clock generator provides a first clock to a first ripple counter of the serializer and a second clock to a second ripple counter of the de-serializer.

Circuit of communication interface between two dies and method to manage communication interface

A testing device includes a transmitter circuit, a receiver circuit, and a loopback circuit. The transmitter circuit is configured to receive a plurality of first test signals. The receiver circuit is configured to receive input data from a plurality of pads in a normal mode. The loopback circuit is coupled to the plurality of pads and input terminals of a sampler circuit, and the loopback circuit is configured to transmit the plurality of first test signals from the transmitter circuit to the input terminals of the sampler circuit, in order to generate test data for subsequent analysis.

Testing device and testing method

A clock data recovery device includes a phase detector circuitry, a signal control circuitry, and interpolators. The phase detector is configured to detect a phase of an input signal, according to first clock signals, to generate first control signals, and phases of the first clock signals are different to each other. The signal control circuitry is configured to rearrange the first control signals to output as second control signals. The phase interpolators are configured to output second clock signals and alternatively adjust the phases of the second clock signals according to the second control signals to generate an output clock signal.

Clock data recovery device and method to alternatively adjust phases of outputted clock signals

An amplifier device includes an amplifier circuitry, a controller circuitry, and an offset cancellation circuitry. The amplifier circuitry is configured to amplify a first input signal and a second input signal, in order to generate a first output signal and a second output signal. The controller circuitry is configured to generate a first control signal and a second control signal according to the first output signal and the second output signal. The offset cancellation circuitry is configured to provide a negative capacitor to the amplifier circuitry, and to adjust at least one current flowing through a circuit, which provides the negative capacitor, of the offset cancellation circuitry according to the first control signal and the second control signal, in order to cancel an offset of the amplifier circuitry.

Amplifier device and offset cancellation method

A multi-channel transceiver includes a phase-locked loop circuit, a first transmitting channel and a second transmitting channel. The phase-locked loop circuit generates a first clock signal set and a second clock signal set with different frequencies. The first transmitting channel includes a first phase adjusting circuit and a first transmitter. The first phase adjusting circuit receives the first clock signal set and generates a first spread spectrum clock signal with a first SSCG profile. According to the first spread spectrum clock signal, the first transmitter generates a first serial data. The second transmitting channel includes a second phase adjusting circuit and a second transmitter. The second phase adjusting circuit receives the second clock signal set and generates a second spread spectrum clock signal with a second SSCG profile. According to the second spread spectrum clock signal, the second transmitter generates a second serial data.

Multi-channel transceiver

A latch circuit including a symmetric circuit, a clock receiving circuit, a current generating circuit, a sampling circuit and a holding circuit is provided. The clock receiving circuit receives a first clock signal and a second clock signal. A phase difference between the first clock signal and the second clock signal is 180 degrees. The current generating circuit is electrically connected with the symmetric circuit and the clock receiving circuit, for providing a discharge current. The sampling circuit is electrically connected with the current generating circuit. According to the first clock signal, the sampling circuit receives a differential input signal, and the discharge current flows through the sampling circuit. The holding circuit is electrically connected with the current generating circuit. According to the second clock signal, the discharge current flows through the holding circuit, and the holding circuit generates a differential output signal.

Current-mode logic latch circuit

An active inductor includes a first transistor, a capacitor, a second transistor, a first resistor, a second resistor, and a bias current source. A source terminal of the first transistor is a first terminal of the active inductor and connected to a first voltage source. The capacitor is connected to the source terminal and gate terminal of the first transistor. A drain terminal of the second transistor is connected to the source terminal of the first transistor. A gate terminal of the second transistor is connected to a drain terminal of the first transistor. The first resistor is connected between the drain terminal of the first transistor and a second terminal of the active inductor. The second resistor is connected to a source terminal of the second transistor. The bias current source is connected between the second resistor and a second voltage source.

Active inductor and associated amplifying circuit

A current-mode D latch includes a first load element, a second load element, a first bias current source, a first switch transistor, a second switch transistor, a first stage circuit and a second stage circuit. The first switch transistor is controlled by an inverted reset signal. The second switch transistor is controlled by a reset signal. When an inverted clock signal is in a first level state and the reset signal is inactive, the first input signal is converted into the first output signal and the first inverted input signal is converted into the first inverted output signal by the first stage circuit. When a clock signal is in the first level state and the reset signal is inactive, the first output signal and the first inverted output signal are maintained by the second stage circuit.

Current-mode D latch with reset function and associated circuit

An oscillation circuit and associated method, wherein the oscillation circuit provides a pair of oscillation signals at two oscillation nodes, and includes a first capacitor, a switch circuit and a second capacitor serially coupled between the two oscillation nodes; the switch circuit conducts between the first capacitor and the second capacitor on an enable voltage higher than a power voltage of the oscillation circuit.

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Hsinchu, Taiwan

Tsai-Ming Yang