Phison Electronics Corporation

Tsai-Hao Kuo

Wei Hung Lin

Riichiro Shirota

Yu-Cheng Hsu

Nina Mitiukhina

Yu-Siang Yang

Szu-Wei Chen

An-Cheng Liu

Hsiao-Yi Lin

Lih Yuarn Ou

A memory management method, a memory storage device, and a memory control circuit unit are provided. The method includes: reading first data from a first physical unit by using a first read voltage level according to first management information among multiple candidate management information; decoding the first data and recording first error bit information of the first data; and adjusting sorting information related to the candidate management information according to the first error bit information. The sorting information reflects a usage order of the candidate management information in a decoding operation.

Memory management method, memory storage device, and memory control circuit unit

A voltage adjusting method, a memory controlling circuit unit and a memory storage device are provided. The method includes: reading a first physical programming unit in a first physical programming unit group to obtain first data; correcting the first data according to a first error check and correction code corresponding to the first data to obtain first corrected data; reading a second physical programming unit in the first physical programming unit group to obtain second data; and adjusting a first read voltage for reading a first memory cell to a second read voltage according to the first data, the first corrected data, and the second data.

Voltage adjusting method, memory controlling circuit unit and memory storage device

A NAND flash memory unit is described, including a string of memory cells connected in series, S/D regions coupled to two terminals of the string, at least one select transistor couple between a terminal of the string and an S/D region, and at least one erase transistor couple between the at least one select transistor and an S/D region. The select transistor is for selecting the string of memory cells. The erase transistor is for reducing Vt-shift of the select transistor.

NAND flash memory unit and NAND flash memory array

NAND flash memory unit, NAND flash memory array, and methods for operating them

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Tainan, Taiwan

Tsai-Hao Kuo