United Microelectronics Corp.

Taiwan Semiconductor Manufacturing Comp. Ltd.

Tsai-Fu Hsiao

Chin-Cheng Chien

Hsiang-Ying Wang

Chao-Chun Chen

Po-Yuan Chen

Tze-Liang Lee

Ching-I Li

Chun-An Lin

Clement Hsingjen Wann

Yi-Wei Chen

Pei-Ren Jeng

Neng-Kuo Chen

Kuang-Yuan Hsu

Sey-Ping Sun

Shu-Yen Chan

Gin-Chen Huang

Ching-Hong Jiang

Hongfa Luan

Ming-Yen Chien

Teng-Chun Tsai

Tai-Chun Huang

Yu-Ren Wang

Shyh-Fann Ting

Cheng-Tung Huang

Chien-Chung Huang

Kuo-Tai Huang

Meng-Yi Wu

Tzyy-Ming Cheng

Wen-Han Hung

Tsuo-Wen Lu

Kun-Hsien Lee

Chao-Ching Hsieh

Jei-Ming Chen

Li-Shian Jeng

Yu-Lan Chang

Chun-Chieh Chang

Chun-Yao Wang

Tsung-Yu Hung

Jung-Chin Chen

An apparatus includes a vacuum chamber, a wafer transfer mechanism, a first gas source, a second gas source and a reuse gas pipe. The vacuum chamber is divided into at least three reaction regions including a first reaction region, a second reaction region and a third reaction region. The wafer transfer mechanism is structured to transfer a wafer from the first reaction region to the third reaction region via the second reaction region. The first gas source supplies a first gas to the first reaction region via a first gas pipe, and a second gas source supplies a second gas to the second reaction region via a second gas pipe. The reuse gas pipe is connected between the first reaction region and the third reaction region for supplying an unused first gas collected in the first reaction region to the third reaction region.

Apparatus for manufacturing a thin film and a method therefor

Semiconductor device manufacturing methods and methods of forming insulating material layers are disclosed. In one embodiment, a method of forming a composite insulating material layer of a semiconductor device includes providing a workpiece and forming a first sub-layer of the insulating material layer over the workpiece using a first plasma power level. A second sub-layer of the insulating material layer is formed over the first sub-layer of the insulating material layer using a second plasma power level, and the workpiece is annealed.

Semiconductor device manufacturing methods and methods of forming insulating material layers

A CMOS transistor and a method for manufacturing the same are disclosed. A semiconductor substrate having at least a PMOS transistor and an NMOS transistor is provided. The source/drain of the PMOS transistor comprises SiGe epitaxial layer. A carbon implantation process is performed to form a carbon-doped layer in the top portion of the source/drain of the PMOS transistor. A silicide layer is formed on the source/drain. A CESL is formed on the PMOS transistor and the NMOS transistor. The formation of the carbon-doped layer is capable of preventing Ge out-diffusion.

Method for manufacturing CMOS transistor

A wafer processing chamber is provided, including a first processing gas supply unit and a second processing gas supply unit. The first processing gas supply unit is configured for supplying a first processing gas to form a first processing zone in the wafer processing chamber. The second processing gas supply unit is configured for supplying a second processing gas into the wafer processing chamber to form a second processing zone in the wafer processing chamber. In the wafer processing chamber, the first processing zone and the second processing zone are virtually separated from each other, such that a process wafer in the first processing zone may be performed a different process from another process wafer in the second processing zone at the same time. Further, a heat treatment apparatus and a method for processing wafers also provide herein.

Wafer processing chamber, heat treatment apparatus and method for processing wafers

The invention discloses a method for fabricating a MOS transistor. A substrate having thereon a gate structure is provided. A silicon nitride layer is deposited on the gate structure. A dry etching process is then performed to define a silicon nitride spacer on each sidewall of the gate structure and a recess in a source/drain region on each side of the gate structure. A transitional layer covering the gate structure and the recess is deposited. A pre-epitaxial clean process is performed to remove the transitional layer. The substrate is subjected to a pre-bake process. An epitaxial growth process is performed to grow an embedded SiGe layer in the recess. The disposable silicon nitride spacer is removed.

Method for fabricating MOS transistor

A method for fabricating a metal-oxide semiconductor transistor is disclosed. The method includes the steps of: providing a semiconductor substrate; forming a gate structure on the semiconductor substrate; and performing a first ion implantation process to implant a first molecular cluster having carbon, boron, and hydrogen into the semiconductor substrate at two sides of the gate structure for forming a doped region, wherein the molecular weight of the first molecular cluster is greater than 100.

Method for fabricating metal-oxide semiconductor transistors

A method for fabricating a metal-oxide semiconductor transistor is disclosed. First, a semiconductor substrate having a gate structure thereon is provided, and a spacer is formed around the gate structure. An ion implantation process is performed to implant a molecular cluster containing carbon, boron, and hydrogen into the semiconductor substrate at two sides of the spacer for forming a doped region. The molecular weight of the molecular cluster is preferably greater than 100. Thereafter, a millisecond annealing process is performed to activate the molecular cluster within the doped region.

A method for fabricating strained-silicon transistors is disclosed. First, a semiconductor substrate is provided and a gate structure and a spacer surrounding the gate structure are disposed on the semiconductor substrate. A source/drain region is then formed in the semiconductor substrate around the spacer, and a first rapid thermal annealing process is performed to activate the dopants within the source/drain region. An etching process is performed to form a recess around the gate structure and a selective epitaxial growth process is performed to form an epitaxial layer in the recess. A second rapid thermal annealing process is performed to redefine the distribution of the dopants within the source/drain region and repair the damaged bonds of the dopants.

Method for fabricating strained-silicon metal-oxide semiconductor transistors

A semiconductor process is provided. The semiconductor process includes providing a substrate. Then, a surface treatment is performed to the substrate to form a buffer layer on the substrate. Next, a first pre-amorphous implantation is performed to the substrate.

Semiconductor process

A method of forming a MOS transistor, in which, a co-implantation is performed to implant a carbon co-implant into a source region and a drain region or a halo implanted region to effectively prevent dopants from over diffusion in the source region and the drain region or the halo implanted region, for obtaining a good junction profile and improving short channel effect, and the carbon co-implant is from a precursor comprising CO or CO.

Method of forming a MOS transistor

A salicide process contains providing a silicon substrate that comprises at least a predetermined salicide region, performing a cluster ion implantation process to form an amorphized layer in the predetermined salicide region of the silicon substrate near, forming a metal layer on the surface of the amorphized layer, and reacting the metal layer with the amorphized layer to form a silicide layer on the surface of the silicon substrate.

Salicide process utilizing a cluster ion implantation process

A method for fabricating an NMOS transistor is disclosed. First, a substrate having a gate structure thereon is provided. A carbon implantation process is performed thereafter by implanting carbon atoms into the substrate for forming a silicon carbide region in the substrate. Subsequently, a source/drain region is formed surrounding the gate structure. By conducting a carbon implantation process into the substrate and a corresponding amorphorized implantation process before or after the carbon implantation process is completed, the present invention eliminates the need of forming a recess for accommodating an epitaxial layer composed of silicon carbide while facilitates the formation of silicon carbide from the combination of both implantation processes.

Method for fabricating an NMOS transistor

A method for fabricating a metal-oxide semiconductor transistor is disclosed. First, a semiconductor substrate having a gate structure thereon is provided, and a spacer is formed around the gate structure. An ion implantation process is performed to implant a molecular cluster containing boron into the semiconductor substrate surrounding the spacer for forming a source/drain region. The weight ratio of each boron atom within the molecular cluster is preferably less than 10%. Thereafter, a millisecond annealing process is performed to activate the molecular cluster within the source/drain region.

Growing community of inventors

Hsin-Chu, Taiwan

Tsai-Fu Hsiao