United Microelectronics Corp.

Tsai-Fu Chen

Wen-Han Hung

Ta-Kang Lo

Tzyy-Ming Cheng

Shyh-Fann Ting

Cheng-Tung Huang

Kun-Hsien Lee

Hung-Chang Chang

Shang-Jr Chen

Teng-Chun Tsai

Neng-Kuo Chen

Chien-Chung Huang

Shi-Chung Sun

Cheng-Yu Ma

Chia-Chen Tsai

Shou-Wei Hsieh

Hao-Ming Lee

Chun-Chia Chen

Hsin-Ta Hsieh

Chen-Chien Li

Ching-Sen Lu

Ta Kang Lo

Shuo-Lin Hsu

A high electron mobility transistor (HEMT) device including a substrate, a channel layer, a barrier layer, a p-type gallium nitride (GaN) spacer, a gate electrode, a source electrode, and a drain electrode is provided. The channel layer is disposed on the substrate. The barrier layer is disposed on the channel layer and has a protruding portion. The P-type GaN spacer is disposed on a side wall of the protruding portion. The gate electrode is disposed on the protruding portion and the P-type GaN spacer. The source electrode and the drain electrode are disposed on two sides of the gate electrode.

High electron mobility transistor device having a barrier layer with a protruding portion

A method of manufacturing a semiconductor device is provided in the present invention. Multiple spacer layers are used in the invention to form spacers with different predetermined thickness on different active regions or devices, thus the spacing between the strained silicon structure and the gate structure (SiGe-to-Gate) can be properly controlled and adjusted to achieve better and more uniform performance for various devices and circuit layouts.

Semiconductor device and method of manufacturing the same

A manufacturing method of a semiconductor device includes the following steps. A first gate dielectric layer is formed in a first gate trench and a second gate dielectric layer is formed in a second gate trench. A first bottom barrier layer is formed on the first gate dielectric layer and the second gate dielectric layer. A first conductivity type work function layer is formed on the first bottom barrier layer. A first treatment to the first gate dielectric layer and/or a second treatment to the first bottom barrier layer on the first gate dielectric layer are performed before the step of forming the first conductivity type work function layer. The first treatment and the second treatment are used to modify threshold voltages of specific transistors, and thicknesses of work function layers formed subsequently may be modified for increasing the related process window accordingly.

Manufacturing method of semiconductor device

A semiconductor device and method of manufacturing the same are provided in the present invention. Multiple spacer layers are used in the invention to form spacers with different predetermined thickness on different active regions or devices, thus the spacing between the strained silicon structure and the gate structure (SiGe-to-Gate) can be properly controlled and adjusted to achieve better and more uniform performance for various devices and circuit layouts.

A transistor structure is provided in the present invention. The transistor structure includes: a substrate comprising a N-type well, a gate disposed on the N-type well, a spacer disposed on the gate, a first lightly doped region in the substrate below the spacer, a P-type source/drain region disposed in the substrate at two sides of the gate, a silicon cap layer covering the P-type source/drain region and the first lightly doped region and a silicide layer disposed on the silicon cap layer, and covering only a portion of the silicon cap layer.

Transistor structure

A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a dummy gate on the substrate; forming a contact etch stop layer on the dummy gate and the substrate; performing a planarizing process to partially remove the contact etch stop layer; partially removing the dummy gate; and performing a thermal treatment on the contact etch stop layer.

Method for fabricating semiconductor device

A method for fabricating a metal-oxide-semiconductor field-effect transistor includes the following steps. Firstly, a substrate is provided. A gate structure, a first spacer, a second spacer and a source/drain structure are formed over the substrate. The second spacer includes an inner layer and an outer layer. Then, a thinning process is performed to reduce the thickness of the second spacer, thereby retaining the inner layer of the second spacer. After a stress film is formed on the inner layer of the second spacer and the source/drain structure, an annealing process is performed. Afterwards, the stress film is removed.

Method for fabricating metal-oxide-semiconductor field-effect transistor

A method of fabricating transistors includes: providing a substrate including an N-type well and P-type well; forming a first gate on the N-type well and a second gate on the P-type well, respectively; forming a third spacer on the first gate; forming an epitaxial layer in the substrate at two sides of the first gate; forming a fourth spacer on the second gate; forming a silicon cap layer covering the surface of the epitaxial layer and the surface of the substrate at two sides of the fourth spacer; and forming a first source/drain doping region and a second source/drain doping region at two sides of the first gate and the second gate respectively.

Method of fabricating transistors

A method for fabricating metal gate transistor is disclosed. The method includes the steps of: providing a substrate, wherein the substrate comprises a transistor region defined thereon; forming a gate insulating layer on the substrate; forming a stacked film on the gate insulating layer, wherein the stacked film comprises at least one etching stop layer, a polysilicon layer, and a hard mask; patterning the gate insulating layer and the stacked film for forming a dummy gate on the substrate; forming a dielectric layer on the dummy gate; performing a planarizing process for partially removing the dielectric layer until reaching the top of the dummy gate; removing the polysilicon layer of the dummy gate; removing the etching stop layer of the dummy gate for forming an opening; and forming a conductive layer in the opening for forming a gate.

Metal gate transistor and method for fabricating the same

A transistor structure is provided in the present invention. The transistor structure includes: a substrate comprising a P-type well, a gate disposed on the P-type well, a first spacer disposed on the gate, an N-type source/drain region disposed in the substrate at two sides of the gate, a silicon cap layer covering the N-type source/drain region, a second spacer around the first spacer and the second spacer directly on and covering a portion of the silicon cap layer and a silicide layer disposed on the silicon cap layer.

A method for forming a transistor having a metal gate is provided. A substrate is provided first. A transistor is formed on the substrate. The transistor includes a high-k gate dielectric layer, an oxygen containing dielectric layer disposed on the high-k gate dielectric layer, and a dummy gate disposed on the oxygen containing dielectric layer. Then, the dummy gate and the patterned gate dielectric layer are removed. Lastly, a metal gate is formed and the metal gate directly contacts the high-k gate oxide.

Method of making transistor having metal gate

Method of fabricating transistors and a transistor structure for improving short channel effect and drain induced barrier lowering

A method for fabricating an ultra-high tensile-stressed nitride film is disclosed. A PECVD process is first performed to deposit a transitional silicon nitride film over a substrate. The transitional silicon nitride film has a first concentration of hydrogen atoms. The transitional silicon nitride film is subjected to UV curing process for reducing the first concentration of hydrogen atoms to a second concentration of hydrogen atoms.

Method for fabricating ultra-high tensile-stressed film and strained-silicon transistors thereof

A metal-oxide-semiconductor (MOS) transistor device is disclosed. The MOS transistor device comprises a semiconductor substrate; a gate structure on the semiconductor substrate; source/drain regions on the semiconductor substrate adjacent to the gate structure; an ultra-high tensile-stressed nitride film having a hydrogen concentration of less than 1E22 atoms/cmcovering the gate structure and the source/drain regions; and an inter-layer dielectric (ILD) film over the ultra-high tensile-stressed nitride film.

A process for fabricating electrodes for the capacitor dielectric of semiconductor memory devices with low leakage current characteristics is disclosed. The process comprises the steps of first depositing a titanium oxide film over a semiconductor silicon substrate. The deposited titanium oxide film is then annealed. A layer of tungsten nitride top electrode is then deposited on the annealed titanium oxide film. A second annealing procedure is then conducted to simulate post electrode high temperature process.

Growing community of inventors

Hsinchu, Taiwan

Tsai-Fu Chen