Taiwan Semiconductor Manufacturing Comp. Ltd.

Tsai-Chun Li

Huan-Just Lin

Yu-Lien Huang

Bi-Ming Yen

Cheng-Hua Yang

Huang-Ming Chen

Yang-Cheng Wu

Bao-Ru Young

Wei Cheng Wu

Sheng-Chen Chung

Chun-Ming Hu

Harry-Hak-Lay Chuang

Shih-Chang Chen

Ching-Feng Fu

Ming-Huan Tsai

Yuan-Tien Tu

Yi-Chen Lo

Hak-Lay Chuang

D T Lee

Embodiments of the present disclosure may be used for patterning a layer in a 5 nm node or beyond fabrication to achieve an end-to-end distance below 35 nm. Compared to the state of the art technology, embodiments of the present disclosure reduce cycle time and cost of production from three lithographic processes and four etching processes to one lithographic process and three etch processes.

Methods for controlling an end-to-end distance in semiconductor device

A method of forming a semiconductor device includes forming a source/drain region and spacers on a substrate. The method further includes forming an etch stop layer on the spacers and the source/drain region and forming a gate structure between the spacers. The method further includes etching back the gate structure, etching back the spacers and the etch back layer, and forming a gate capping structure on the etched back gate structure, spacers, and etch stop layer.

Gate structure for semiconductor device

A method of forming a semiconductor device includes forming a dielectric layer over a substrate. The method includes forming a layer set over the dielectric layer, wherein the layer set comprises a plurality of layers. The method further includes forming a bottom antireflective coating (BARC) layer over the layer set. The method further includes etching the layer set to form a tapered opening in the layer set, wherein etching the layer set comprises etching at least one layer comprising a silicon-rich photoresist material layer and a second material layer different from the silicon-rich photoresist material, and the tapered opening has sidewalls at an angle with respect to a top surface of the dielectric layer. The method further includes etching the dielectric layer using the layer set as a mask to form an opening in the dielectric layer, wherein etching the dielectric layer comprises reducing a thickness of the layer set.

Method of making a semiconductor device using a barrier and antireflective coating (BARC) layer

A method of making a semiconductor device includes forming an intermediate semiconductor device. The intermediate device includes a substrate; and a dielectric layer over the substrate. The intermediate device includes a first layer set, including a silicon-rich photoresist material, over the dielectric layer. The intermediate device includes a second layer set, including a carbon-rich organic material layer, over the first layer set. The method further includes etching the second layer set to form a tapered opening in the second layer set. The method further includes etching the first layer set to form an opening in the first layer set, wherein etching the first layer set comprises removing the carbon-rich organic material layer. The method further includes etching the dielectric layer using the first layer set as a mask to form an opening in the dielectric layer, wherein etching the dielectric layer comprises reducing a thickness of the first layer set.

Method of making a semiconductor device using multiple layer sets

This description relates to a method of making a semiconductor device including forming an inter-level dielectric (ILD) layer over a substrate and forming a layer set over the ILD layer. The method further includes etching the layer set to form a tapered opening in the layer set and etching the ILD layer using the layer set as a mask to form an opening in the ILD layer. The opening in the ILD layer has a line width roughness (LWR) of less than 3 nanometers (nm). This description also relates to a semiconductor device including an inter-level dielectric (ILD) layer over a substrate; and a layer set over the ILD layer. The layer set has a tapered opening within the layer set. Etching the layer set comprises forming the tapered opening having sidewalls at an angle with respect to a top surface of the ILD layer ranging from 85-degrees to 90-degrees.

Method of making a semiconductor device using a bottom antireflective coating (BARC) layer

A mechanism for forming a semiconductor device is described. The semiconductor device includes a substrate and an inter-layer dielectric (ILD) layer over the substrate. The intermediate semiconductor device further includes a first layer set over the ILD layer and a second layer set over the first layer set. The intermediate semiconductor device further includes a photoresist layer over the second layer set. The method further includes etching the second layer set to form a tapered opening in the second layer set, the tapered opening having sidewalls at an angle with respect to a top surface of the ILD layer ranging from about 85-degrees to about 90-degrees, but less than 90-degrees. The method further includes etching the first layer set to form an opening in the first layer set and etching the ILD layer using the first layer set as a mask to form an opening in the ILD layer.

An integrated circuit includes a semiconductor substrate including a source region and a drain region and a gate dielectric over the semiconductor substrate. A metal gate structure is over the semiconductor substrate and the gate dielectric and between the source and drain regions. The integrated circuit further includes an interlayer dielectric (ILD) over the semiconductor substrate. First and second contacts extend through the ILD and adjacent the source and drain regions, respectively, and a third contact extends through the ILD and adjacent a top surface of the metal gate structure. The third contact further extends into an undercut region of the metal gate structure.

Contact for high-k metal gate device

A method of making an integrated circuit includes providing a substrate with a high-k dielectric and providing a polysilicon gate structure over the high-k dielectric. A doping process is performed on the substrate adjacent to the polysilicon gate structure, after which the polysilicon gate structure is removed and replaced with a metal gate structure. An interlayer dielectric (ILD) is deposited over the metal gate structure and the doped substrate, and a dry etch process forms a trench in the ILD to a top surface of the metal gate structure. After the dry etch process, a wet etch process forms an undercut near the top surface of the metal gate structure. The trench and undercut are then filled with a conductive material.

Contact for high-K metal gate device

The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a layer over a substrate. The method includes forming a first opening in the layer that exposes a first region of the substrate. The method includes removing a first oxidation layer formed over the first region through a first sputtering process. The method includes filling the first opening with a conductive material. The method includes forming a second opening in the layer that exposes a second region of the substrate, the second region being different from the first region. The method includes removing a second oxidation layer formed over the second region through a second sputtering process. One of the first and second sputtering processes is more powerful than the other.

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Hsinchu, Taiwan

Tsai-Chun Li