Rambus Inc.

Intel Corporation

Trung Am Diep

Hongzhong Zheng

Hong Wang

Gautham N Chinya

Richard A Hankins

Baiju V Patel

Prashant Sethi

Bryant E Bigbee

Shivnandan D Kaushik

John P Shen

Frederick Abbott Ware

Brian S Leibowitz

Xiang Chris Zou

Xinmin Tian

James Paul Held

Paul M Petersen

Pradeep Batra

Sanjiv M Shah

Ryan N Rakvic

Eric Linstadt

John Eric Linstadt

Milind Baburao Girkar

John Thomas Shen

Asit K Mallick

Guei-Yuan Lueh

Brent Steven Haukness

Steven Cameron Woo

Thomas A Piazza

Aditya Sreenivas

Wishwesh Anil Gandhi

Anil Aggarwal

Gansha Wu

J James Tringali

Steve John Clohset

John L Reid

Tuong P Trieu

Michael T Ching

Shih-wei Liao

Shiv Kaushik

Chiv Kaushik

Millind Girkar

Tian Xinmin

A cache memory includes cache lines to store information. The stored information is associated with physical addresses that include first, second, and third distinct portions. The cache lines are indexed by the second portions of respective physical addresses associated with the stored information. The cache memory also includes one or more tables, each of which includes respective table entries that are indexed by the first portions of the respective physical addresses. The respective table entries in each of the one or more tables are to store indications of the second portions of respective physical addresses associated with the stored information.

Methods and apparatuses for addressing memory caches

The disclosed embodiments relate to a computer system with a cache memory that supports tagless addressing. During operation, the system receives a request to perform a memory access, wherein the request includes a virtual address. In response to the request, the system performs an address-translation operation, which translates the virtual address into both a physical address and a cache address. Next, the system uses the physical address to access one or more levels of physically addressed cache memory, wherein accessing a given level of physically addressed cache memory involves performing a tag-checking operation based on the physical address. If the access to the one or more levels of physically addressed cache memory fails to hit on a cache line for the memory access, the system uses the cache address to directly index a cache memory, wherein directly indexing the cache memory does not involve performing a tag-checking operation and eliminates the tag storage overhead.

Cache memory that supports tagless addressing

Embodiments are disclosed for replacing one or more pages of a memory to level wear on the memory. In one embodiment, a system includes a page fault handling function and a memory address mapping function. Upon receipt of a page fault, the page fault handling function maps an evicted virtual memory address to a stressed page and maps a stressed virtual memory address to a free page using the memory address mapping function.

Wear leveling in a memory system

Embodiments related to a cache memory that supports tagless addressing are disclosed. Some embodiments receive a request to perform a memory access, wherein the request includes a virtual address. In response, the system performs an address-translation operation, which translates the virtual address into both a physical address and a cache address. Next, the system uses the physical address to access one or more levels of physically addressed cache memory, wherein accessing a given level of physically addressed cache memory involves performing a tag-checking operation based on the physical address. If the access to the one or more levels of physically addressed cache memory fails to hit on a cache line for the memory access, the system uses the cache address to directly index a cache memory, wherein directly indexing the cache memory does not involve performing a tag-checking operation and eliminates the tag storage overhead.

A memory controller encrypts contents of a page frame based at least in part on a frame key associated with the page frame. The memory controller generates a first encrypted version of the frame key based at least in part on a first process key associated with a first process, wherein the first encrypted version of the frame key is stored in a first memory table associated with the first process. The memory controller generates a second encrypted version of the frame key based at least in part on a second process key associated with a second process, wherein the second encrypted version of the frame key is stored in a second memory table associated with the second process, the first process and the second process sharing access to the page frame using the first encrypted version of the frame key and the second encrypted version of the frame key, respectively.

Process authenticated memory page encryption

Described are systems and method for protecting data and instructions shared over a memory bus and stored in memory. Independent and separately timed stream ciphers for write and read channels allow timing variations between write and read transactions. Data and instructions can be separately encrypted prior to channel encryption to further secure the information. pad generators and related cryptographic circuits are shared for read and write data, and to secure addresses. The cryptographic circuits can support variable data widths, and in some embodiments memory devices incorporate security circuitry that can implement a shared-key algorithm using repurposed memory circuitry.

Methods and circuits for securing proprietary memory transactions

Growing community of inventors

San Jose, CA, United States of America

Trung Am Diep