Megamos Corporation

California Institute of Technology

The United States of America As Represented by the Administrator of the

Applied Materials, Inc.

Magepower Semiconductor Corp.

Magemos Corporation

True-Lon Lin

Fwu-Iuan Hshieh

Koon Chong So

Yan Man Tsui

Danny Chi Nim

Sarath D Gunapala

Jin S Park

John K Liu

Robert W Fathauer

Mani Sundaram

Chentsau Chris Ying

Jeng H Hwang

Kai-Wei Nieh

Steve S Y Mak

Eric W Jones

Paula J Grunthaner

Fwu-Juan Hshieh

Hector M Del Castillo

Shu-Hui Cheng

John W Schaller

A method of etching a noble metal electrode layer disposed on a substrate to produce a semiconductor device including a plurality of electrodes separated by a distance equal to or less than about 0.35 &#x3bc;m and having a noble metal profile equal to or greater than about 80&#xb0;. The method comprises heating the substrate to a temperature greater than about 150&#xb0; C., and etching the noble metal electrode layer by employing a high density inductively coupled plasma of an etchant gas comprising a gas selected from the group consisting of nitrogen, oxygen, a halogen (e.g., chlorine), argon, and a gas selected from the group consisting of BCl, HBr, and SiClmixtures thereof. Masking methods and etching sequences for patterning high density RAM capacitors are also provided.

Masking methods and etching sequences for patterning electrodes of high density RAM capacitors

An Al Ga As/GaAs/Al Ga As quantum well exhibiting a bound-to-quasibound intersubband absorptive transition is described. The bound-to-quasibound transition exists when the first excited state has the same energy as the &ldquo;top&rdquo; (i.e., the upper-most energy barrier) of the quantum well. The energy barrier for thermionic emission is thus equal to the energy required for intersubband absorption. Increasing the energy barrier in this way reduces dark current. The amount of photocurrent generated by the quantum well is maintained at a high level.

Infrared radiation-detecting device

An Al,Ga,As/GaAs/Al,Ga,As quantum well exhibiting a bound-to-quasibound intersubband absorptive transition is described. The bound-to-quasibound transition exists when the first excited state has the same energy as the &ldquo;top&rdquo; (i.e., the upper-most energy barrier) of the quantum well. The energy barrier for thermionic emission is thus equal to the energy required for intersubband absorption. Increasing the energy barrier in this way reduces dark current. The amount of photocurrent generated by the quantum well is maintained at a high level.

Improved power MOSFET structure, and fabrication process are disclosed in this invention to achieve cost savings by simplified device structure and fabrication processes, and also by reducing the required die size. Specifically, in a novel MOSFET device, insulation of mobile ions are achieved by extending the poly gate and metal contacts such that the passivation layer is no longer required and the fabrication process is simplified such that the MOSFET device can be manufactured at a lower price. Furthermore, in another MOSFET device, the gate runner is used to replace the field plate such that the requirement of a field plate as that in a conventional MOSFET device is also eliminated and, by reducing the die size, the cost of manufacture is further reduced.

Cost savings for manufacturing planar MOSFET devices achieved by

The present invention includes a substrate of a first conductivity type having a top surface including at least two intersecting trenches disposed therein with an insulating layer lining the trenches and a conductive material filling the trenches. The transistor also includes a source region of the first conductivity type extending from the top surface of the substrate adjacent to the trenches toward the substrate. The transistor further has a body region of a second conductivity type of opposite polarity from the first conductivity type, the body region extends from the top surface adjacent from the trenches to the substrate and surrounding the source region. The conductive material filling the trenches including punch-through suppressing blocks covering corners of the cell defined by the intersecting trenches wherein the source region disposed underneath the corners immediately next to the trenches having a lower net concentration of impurities of the first conductivity type than remaining portion of the source region.

Punch-through prevention in trenched DMOS with poly-silicon layer

This invention discloses a MOSFET device in a semiconductor chip with a top surface and a bottom surface. The MOSFET device includes a drain region, doped with impurities of a first conductivity type, formed in the semiconductor chip near the bottom surface. The MOSFET device further includes a vertical pn-junction region, which includes a lower-outer body region, doped with impurities of a second conductivity type, formed on top of the drain region. The pn-junction region further includes a source region, doped with impurities of the first conductivity type, formed on top of the lower-outer body region wherein the lower-outer body region defining a channel region extending from the source region to the drain region near the top surface. The MOSFET device further includes a gate formed on top of the channel region on the top surface. The gate includes a thin insulative bottom layer for insulating from the channel region. The gate is provided for applying a voltage thereon for controlling a current flowing from the source region to the drain region via the channel region. The MOSFET device further includes a deep heavily doped body-dopant region disposed immediately below the source region in the lower-outer body region. It is implanted with a higher concentration of dopant than the lower-outer body region whereby a device ruggedness of the MOSFET device is improved. The deep heavily-doped body-dopant region having a body-dopant concentration profile defined by a diffusion of the body-dopant from an implant depth about twice as that of a source implant-depth whereby the deep heavily-doped body dopant region is kept at a distance away from the channel region.

Power MOSFET device manufactured with simplified fabrication processes

The present invention discloses a MOSFET transistor supported on a substrate. The MOSFET transistor includes an epitaxial-layer of a first conductivity type near a top surface of the substrate defining a drain region therein. The MOSFET transistor further includes an oxide block supported on a raised silicon terrace of the epitaxial layer disposed in a central portion of the transistor above a JFET reduction region of a first conductivity type of higher dopant concentration than the epitaxial layer. The MOSFET transistor further includes a lower-outer body region of a second conductivity type surrounding the JFET reduction region disposed near the top surface and defining a boundary of the MOSFET transistor. The MOSFET transistor further includes a source region of the first conductivity type enclosed in the lower-outer body region disposed near the top surface and extended to the transistor boundary. The MOSFET transistor further includes a thin gate oxide layer overlying the top surface of the substrate and an edge of the raised oxide terrace. The MOSFET transistor further includes a polysilicon gate overlaying the oxide block and the silicon terrace, the gate further covering an area above the source region and the body region insulated by the gate oxide layer therefrom.

Self-aligned and process-adjusted high density power transistor with

This invention discloses a MOSFET device which includes a plurality of vertical cells each includes a source, a drain, and a channel for conducting source-to-drain current therethrough. Each of the vertical cells is surrounded by a polysilicon layer acting as a gate for controlling the source-to-drain current through the channel. The MOSFET device further include a plurality of doping trenches filled with trench-filling materials, The MOSFET device further includes a plurality of deep-doped regions disposed underneath the doping trenches wherein the deep-doped region extends downwardly to a depth which is substantially a sum of an implant depth of the deep-doped region and a vertical diffusion depth below a bottom of the doping trenches.

MOSFET structure and fabrication process implemented by forming deep and

The present invention discloses a power transistor disposed on a substrate. The power device includes a core cell area comprising a plurality of power transistor cells each having drain and a source. Each of the power transistor cells further having a polycrystalline silicon gate formed on the substrate as part of a polycrystalline silicon gate layer overlaying the substrate. The polycrystalline silicon gate layer includes a plurality of polycrystalline gate-layer-extension extending to gate contact areas for forming gate contacts with a contact metal disposed thereon. The power transistor further includes a plurality of contact-metal-resistant pad each includes a thick oxide pad disposed below the gate contact areas underneath the polycrystalline gate layer extension whereby the contact-metal resistant pads resists the contact metal from penetrating therethrough and short to the substrate disposed thereunder.

Gate-contact structure to prevent contact metal penetration through gate

Improved power MOSFET structure, and fabrication process are disclosed in this invention to achieve higher breakdown voltage and improved device ruggedness. The power transistor includes a core cell area which includes a plurality of power transistor cells and a termination area. The power transistor further includes an outer pickup guarding ring, disposed in the termination area guarding the core cell area, for picking up free charged-particles generated in the termination area for preventing the free charged particles from entering the core cell area. In another preferred embodiment, the power transistor further includes an inner pickup guarding fence and blocks, disposed between the termination area and the core cell area for picking up free charged-particles not yet picked up by the outer pickup guarding ring for preventing the free charged particles from entering the core cell area.

Mosfet termination design and core cell configuration to increase

A MOSFET device formed in a semiconductor chip with a top surface and a bottom surface. The MOSFET device includes a drain region doped with impurities of a first conductivity type, formed near the bottom surface. The MOSFET device further includes a plurality of vertical cells wherein each of the vertical cell includes a vertical pn-junction zone region includes a lower-outer body region, doped with impurities of a second conductivity type, formed on top of the drain region. The pn-junction region further includes a source region, doped with impurities of the first conductivity type, formed on top of the lower-outer body region, the lower-outer body region surrounding the source region and extending to the top surface thus defining a cell area for the cell. The vertical cell further includes a source contact formed on the top surface contacting the source region. The MOSFET further includes a plurality of gates. Each gate is formed on the top surface as a poly layer extending from an area near a boundary of the source region and the lower-outer body region of one of the cells to a neighboring cell, the gate includes a thin insulative bottom layer for insulating from the vertical cell, the gate is provided for applying a voltage thereon for controlling a charge state of a channel underneath each of the gates thus controlling a vertical current from the source contact to the drain region. The MOSFET device further includes a plurality of open stripes whereby a width of the channel is increased and a JFET resistance for each of the vertical cells is decreased.

Power MOSFETs and cell topology

DMOS transistors having trenched gate oxide

A n-channel MOSFET device is formed with a selective high energy boron implantation into the N region of the n- channel where a photoresist is employed to cover the central portion over the channel. Small n- regions are formed near the channel source interface. These small n- regions have the advantages of preventing punch through. The selective implant regions have the additional advantages that the JFET resistance is not increased as a result of forming a punch through prevention region near the source channel boundary. Also disclosed in this invention is a p-type DMOS where a novel boron implantation is applied to reduce the threshold voltage. The boron is selectively implanted into the n-type channel near the source, i.e., a threshold sensitive region. The threshold voltage is reduced without unduly lowering the drain to source breakdown voltage.

MOSFET transistor cell manufactured with selectively implanted punch

Improved power MOSFET structure, and fabrication process are disclosed in this invention to achieve a low threshold voltage. The improved MOSFET device is formed in a semiconductor substrate with a drain region formed near a bottom surface of the substrate supporting a plurality of double-diffused vertical cells thereon wherein each of the vertical cells including a pn-junction having a body region surrounding a source region and each of the vertical cell further including a gate above the pn-junction. Each of the vertical cells further includes a source-dopant segregation reduction layer for reducing a surface segregation between the source region and an oxide layer underneath the gate whereby the body surface peak dopant concentration near an interface between the source region and the body region is reduced for reducing a threshold voltage of the MOSFET device. In another preferred embodiment, the source-dopant segregation reduction layer includes a LPCVD nitride layer formed on top of the polysilicon gates.

MOSFET structure and fabrication process for decreasing threshold voltage

A new DMOS fabrication process is disclosed. The fabrication process includes the steps of (a) growing an oxide layer on the substrate; (b) applying a first mask to define an active area and for selectively patterning the oxide layer for keeping a plurality of source implant blocking stumps near a plurality source regions wherein the blocking stumps being formed with width greater than twice a diffusion length of a source dopant and with width less than twice a diffusion length of the body dopant whereby the body regions merging together in the body diffusion becoming a single body region underneath the blocking stumps; (c) applying a second mask for forming a plurality of gates covering a portion of areas between the blocking stumps defining an implant window; (d) implanting a body dopant through the implant window followed by a body diffusion for forming a body region underneath the blocking stumps; (e) implanting the source dopant through the implant window over the source implant blocking stumps following by a source diffusion for forming separate source regions underneath the blocking stumps; (f) depositing an insulating dielectric BPSG/PSG layer; (g) employing a contact mask for etching through the insulating dielectric BPSG/PSG layer and the source implant blocking stumps to define contact windows; (h) depositing a metal layer to form a contact layer through the contact window; and (i) patterning the metal layer with a metal contact to define a plurality of contacts whereby the transistor is fabricated with a four masks process.

Growing community of inventors

Cupertino, CA, United States of America

True-Lon Lin