Synopsys, Inc.

Troy W Barbee, Iii

Ross Alexander Donelly

William Clark Naylor, Jr

Uzzal Kumar Bhaumik

Cells in a superconducting electronics (SCE) netlist may be levelized. The SCE may use multiple clock phases, and each level in the levelized SCE netlist may be associated with a clock phase. Buffers may be inserted in the SCE netlist so that output ports of the SCE netlist are associated with the same clock phase. A floorplan may be created for the SCE netlist. A placed SCE netlist may be generated based on the floorplan, where cells in each row of the placed SCE netlist may be clocked using the same clock phase.

Adiabatic quantum-flux-parametron placement

A method and system of placing cells of an IC design using partition preconditioning. In one embodiment, cells of an integrated circuit design are grouped to model curvature of an objective function. The grouping produce a plurality of cell clusters. The model formed may be a binary tree. The curvature of the objective function for each of the cell clusters is estimated. Interactions between said cell clusters are described as a relation. A set of preconditioning values which achieves a separation of variables of the relation is determined. The preconditioning may be applied to a conjugate gradient placement process to advantageously decrease the number of iterations required to produce an optimized placement of the cells.

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Sunnyvale, CA, United States of America

Troy W Barbee, Iii