Synopsys, Inc.

Troy Nathan Gilliland

Yanyi Liu Wong

Andrew Edward Horch

Agustinus Sutandi

Martin L Niset

Rebecca Shiu Yun Cheng

Ross Peterson

Vikramaditya Kundur

Yanyi L Wong

A non-volatile memory system includes an array of bit cells arranged in rows and columns and configured to store bits of data, a reference bit cell, a plurality of bit lines connectable to the bit cells in the array and connecting to the reference bit cell, and a bit line controller. The bit line controller comprises a plurality of sense amps connected to the bit cells by the bit lines. The bit line controller determines the contents of the bit cells based on times tcompared to a time t, where tis the time required for a current Igenerated by one of the bit cells to raise a voltage Vof one of the sense amps by an amount &#x394;V, and tis the time required for a current Igenerated by the reference bit cell to raise the voltage Vof another one of the sense amps by the same &#x394;V. &#x394;V increases monotonically as a function of I.

Non-volatile memory with single ended read scheme using distributed common mode feedback

A circuit provides a regulated voltage supply for other circuits. The circuit includes a bias current source and a reference voltage source. The circuit includes a pass transistor and a feedback transistor. The pass transistor receives input from the feedback transistor that generates a regulated voltage at a terminal of the pass transistor. The feedback transistor receives inputs from the regulated voltage of the pass transistor and the reference voltage source. The feedback transistor provides voltage for the input of the pass transistor, thereby controlling the regulated voltage generated by the pass transistor. The regulated voltage generated by the pass transistor is provided as a regulated voltage supply to other circuits.

Regulated voltage supply with low power consumption and small chip area

A nonvolatile memory ('NVM') bitcell includes a capacitor, a transistor, and a tunneling device. The capacitor, transistor, and tunneling device are each electrically coupled to different active regions and metal contacts. The three devices are coupled by a floating gate that traverses the three active regions. The tunneling device is used to program and erase the device, allowing for faster page erasure, and thus allows for rapid testing and verification of functionality. The transistor is used to read the logical state of the floating gate. The capacitor and floating gate are capacitively coupled together, removing the need for a separate selection device to perform read, write, and/or erase operations.

NVM device using FN tunneling with parallel powered source and drain

Methods and systems for storing data are disclosed. The systems are configured to perform the methods and the methods may include, for example, receiving electronic data to be stored, partitioning the data into multiple segments, and storing each segment in a memory during a separate write cycle. The methods may also include programming a compensation load so that power provided by a power supply during the storing of each segment is substantially the same.

Memory power supply load management

Controlling a non-volatile memory. The non-volatile memory includes a plurality of memory cells in an integrated circuit substrate. The non-volatile memory also includes a high-voltage node in power-transmissive communication with the plurality of memory cells. Further, the non-volatile memory includes an intermediate-voltage node in power-transmissive communication with the plurality of memory cells. Moreover, the non-volatile memory includes a counter-doped-gate device, coupled within the integrated circuit substrate, in power-transmissive communication between the high-voltage node and the intermediate-voltage node.

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Bellevue, WA, United States of America

Troy Nathan Gilliland