International Business Machines Corporation

Other

Globalfoundries Inc.

Troy James Beukema

Scott Kevin Reynolds

Matthew B Baecher

Lamiaa Msalka

Sergey Vladimirovich Rylov

William Richard Kelly

Thomas Helmut Toifl

John Francis Bulzacchelli

Brian Allan Floyd

Mihai A Sanduleanu

Yong Liu

Zeynep Toprak Deniz

Martin Cochet

Gautam Gangasani

Alberto Valdes Garcia

Brian Paul Gaucher

Michael Anthony Sorna

Marcel A Kossel

Jonathan E Proesel

Young Hoon Kwark

Jonas R Weiss

Mounir Meghelli

Michael Frank Cina

Modest M Oprysko

Steven Mark Clements

Ephraim Bemis Flint

Daniel W Storaska

Saila Ponnapalli

William Edward Pence, Iv

Chun-Ming Hsu

Elizabeth M May

A data equalization system includes a data clock input configured to receive a clock signal. There is an input node operative to receive a data signal of transmission symbols that change state synchronously with the clock signal. There is a first tap coupled to the input node. A second tap is configured to receive a variation of the data signal. At least one of a weight of the first tap or a weight of the second tap is modulated by a dynamic control parameter that repeats synchronously with each transmission symbol.

Time dependent line equalizer for data transmission systems

Devices, systems, and methods that can facilitate in situ probing of a discrete time circuit components are provided. According to an embodiment, a device can comprise a hold circuit that can generate a sampled signal at a holding stage. The device can further comprise an in situ probe device that can be coupled to the hold circuit that can measure one or more operating voltage values at the holding stage based on the sampled signal.

In situ probing of a discrete time analog circuit

An apparatus includes an FFE circuit, including a clock generator creating multiple sub-rate phases of an input clock, and a multi-phase sampler responsive to a data signal and to the multiple sub-rate phases generated by the clock generator. The sampler is configured to sample the data signal and to generate held sample outputs corresponding to the multiple sub-rate phases. A SC equalization circuit in the FFE circuit has two states and is responsive to inputs from the multi-phase sampler output and the clock generator. The SC equalization circuit is configured to form outputs using the two states. A variable gain output stage in the FFE circuit is responsive to the outputs from the SC equalization circuit and is responsive to gain control signal(s) to provide variable gains to corresponding outputs of the SC equalization circuit to form equalized outputs based on the data signal.

Integrated switched-capacitor-based analog feed-forward equalizer circuits

A single-ended inter-chip data transmission system and a single-ended inter-chip data reception system are provided for processing data. A controlled Hamming weight parallel data encoder at a transmitter device accepts N data bits with an arbitrary Hamming weight as input and generates M data bits with a controlled Hamming weight as output, wherein M is greater than N. A transmission circuit provides a time-aligned transmission of the controlled Hamming weight encoded data across a single-ended data bus.

Inter-chip data transmission system using single-ended transceivers

A dynamic tap weight generator circuit includes a clock generator circuit having a first output and a second output. There is a current interpolator circuit coupled to a first current source and a second current source and to the first and second outputs of the clock generator circuit and operative to provide a first output and a second output providing a differential output current between a current of the first current source and a current of the second current source across a symbol transmission interval. A 2:1 current multiplexer is coupled to a first and second outputs of the current interpolator circuit. A tap weight driver is coupled to an output of the 2:1 current multiplexer and configured is to dynamically adjust a tap weight of an equalizer dynamically during each clock cycle of the clock generator.

A device can comprise a peaked integrator circuit that generates an output signal from a continuous time signal based on a sub rate clock timing cycle. The device can further comprise a track and hold circuit coupled to the output of the peaked integrator that generates a held discrete time signal from the output of the peaked integrator based on a second sub rate clock timing cycle that is offset in time from the sub rate clock timing cycle by a single time unit interval. The device can further comprise an integrator circuit coupled to an output of the track and hold circuit that integrates the held discrete time signal, based on the second sub rate clock timing cycle that is offset in time from the sub rate clock timing cycle by a single time unit interval.

Discrete time analog front end circuit implemented in a receiver device

P and N termination networks couple a P line and an N line to corresponding receiver inputs. Each termination network includes an electrostatic discharge protection T-coil having an input port coupled to the corresponding line, a terminal port, and a center tap port. At least one of the termination networks further includes at least one delay T-coil having a terminal port, a center tap port, and an input port coupled to the terminal port of a corresponding one of the electrostatic discharge protection T-coils. In a no delay mode, a multiplexer selectively connects the P and N electrostatic discharge protection T-coil center tap ports to the P and N inputs of the receiver. In a delay mode, the multiplexer selectively connects the delay T-coil center tap port to a corresponding one of the P input of the receiver and the N input of the receiver.

Differential line time skew compensation for high data rate receivers

Various embodiments of the present invention solve the problem of generating intermediate-time information useable to drive ZFE adaptation (for example, in connection with a digital receiver). Further, various embodiments of the present invention increase flexibility by enabling user-specified over-peaking and/or under-peaking (i.e. configurable equalizer tuning) with respect to a ZFE convergence (or lock) criterion.

System, method and software program for tuneable equalizer adaptation using sample interpolation

Digital receiver systems and clock recovery techniques for use in digital receiver systems are provided to implement asynchronous baud-rate clock recovery systems for high data rate serial receivers multilevel line modulation. A two-stage postcursor ISI equalization system is provided to efficiently emulate a 4-level DFE (decision feedback equalization) system, for example, while converting a 4-level equalized signal to s 2-level equalized signal. For example, a two stage postcursor ISI equalization system includes a DFE stage which operates on a most significant component of a given 4-level data symbol, followed by a DFFE (decision-feedforward equalizer) stage which operates on a least significant component of the given 4-level data symbol. In parallel with the DFFE stage, an estimate of the least significant component is subtracted from the equalized 4-level data symbol to convert the 4-level data symbol to a 2-level symbol.

High data rate multilevel clock recovery system

An analog-to-digital converter includes a plurality of slave sampler multiplexers responsive to outputs of a master sampler that receives analog signals and whose output ports connect to integrating threshold comparators having capacitive digital-to-analog conversion offset adjustments for forming an analog-to-thermometer code conversion. A calibration state machine receives outputs of each of the integrating threshold comparators to control the capacitive digital-to-analog conversion offset adjustment of every integrating threshold comparator and to control a calibration digital-to analog converter. A thermometer code to binary code logic decoder receives outputs of each of the integrating threshold comparators and outputs digital samples.

Analog to digital converter with high precision offset calibrated integrating comparators

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Briarcliff Manor, NY, United States of America

Troy James Beukema