Agilent Technologies, Inc.

Avago Technologies General IP (singapore) Pte. Ltd.

Avago Technologies General IP Pte, Ltd.

Avago Technologies Enterprise IP (singapore) Pte. Ltd.

Troy Horst Frerichs

Richard S Rodgers

Howard L Porter

Ryan Korzyniowski

Victoria Meier

Systems and methods are disclosed herein for determining the placement of a standard cell, representing a semiconductor component in a design stage, on an integrated circuit die. One embodiment of a method, among others, comprises analyzing regions of a semiconductor die with respect to the susceptibility of the region to be exposed to radiation. This method further comprises placing the standard cell in one of the analyzed regions of the semiconductor die, the standard cell being placed based on the sensitivity of the standard cell to radiation. The method may also comprise running an algorithm, e.g. using a component placement engine, for determining the placement of semiconductor components on an integrated circuit die.

Determining the placement of semiconductor components on an integrated circuit

Systems and methods are disclosed herein for determining the placement of storage and non-storage cells or components, representing a semiconductor component in a design stage, on an integrated circuit die. In one embodiment, regions of a semiconductor die are analyzed with respect to the susceptibility of a region to be exposed to radiation and the distance between a storage component and a local clock buffer. The radiation, for instance, may be alpha particle radiation emitted from lead (Pb) isotopes in solder bumps formed on the integrated circuit die. The distance, spatial positioning and/or physical proximity of a selected local clock buffer and a storage component are preferably selected so that the skew between the storage component and the local clock buffer is about 30 picoseconds or less. Other maximum skews may be employed, however, such as about 100 picoseconds or less, about 90 picoseconds or less, about 80 picoseconds or less, about 70 picoseconds or less, about 60 picoseconds or less, about 50 picoseconds or less, about 40 picoseconds or less, about 20 picoseconds or less, about 10 picoseconds or less and about 5 picoseconds or less.

Alpha-particle-tolerant semiconductor die systems, devices, components and methods for optimizing clock rates and minimizing die size

A clock driver placement system and method are provided to place clock drivers in a standard cell block. In accordance with one aspect of the invention, a system is provided for placing clock drivers in a standard cell block. The system operates using logic that establishes an initial clock driver placement pattern, and logic that determines a number of clock drivers needed in the standard cell block to comply with a time specification. The system also includes a logic that adds clock drivers to the standard cell block using the initial clock driver placement pattern. In accordance with another aspect of the invention, a method establishes an initial clock driver placement pattern and determines a number of clock drivers needed in the standard cell block to comply with a time specification. Then, the clock drivers are added to the standard cell block using the initial clock driver placement pattern.

System and method for placing clock drivers in a standard cell block

A substrate contact placement system and method are provided for the placement of substrate contacts in a datapath stack in an integrated circuit design. In accordance with one aspect of the invention, a system establishes a floorplan for the datapath stack containing a plurality of datapath macros in a netlist, and determines a placement of substrate contacts for a datapath macro in the datapath stack to minimize area used for the substrate contacts. Then, the system adds substrate contacts to the datapath stack. In accordance with another aspect of the invention, a method includes establishing a floorplan for the datapath stack containing a plurality of datapath macros in a netlist, and determining a placement of substrate contacts for a datapath macro in the datapath stack to minimize area used for the substrate contacts. Then, the substrate contacts are added to the datapath stack.

System and method for placing substrate contacts in a datapath stack in an integrated circuit design

An electrical rules checker system and method provides for correcting charge collector violations in a netlist. In accordance with one aspect of the invention, the electrical rules checker system includes a charge collector violation correction mechanism that includes a logic for analyzing the circuit configuration in a netlist, and a logic for identifying a charge collector violation in the circuit configuration. The charge collector violation correction mechanism further includes a logic for adding a charge collector diode to the netlist to correct the charge collector violation in the circuit configuration. In accordance with another aspect of the invention, a method analyzes the circuit configuration in a netlist, and identifies a charge collector violation in the circuit configuration. A charge collector diode is then added to the netlist to correct the charge collector violation in the circuit configuration.

System and method for correcting charge collector violations

A clock buffer placement system and method are provided for the placement of clock buffers in a datapath stack. In accordance with one aspect of the invention, the system positions at least one track beside the datapath stack in a netlist, and identifies placement of clock buffers needed in the at least one track. Then, the system modifies the netlist by connecting at least one datapath macro to the clock buffers on the at least one track. In accordance with another aspect of the invention, a method includes positioning at least one track beside the datapath stack in a netlist, and identifying placement of clock buffers needed in the at least one track. Then, the netlist is modified by connecting at least one datapath macro to the clock buffers on the at least one track.

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Fort Collins, CO, United States of America

Troy Horst Frerichs