Hitachi, Ltd.

Texas Instruments Corporation

Other

Troy H Herndon

Goro Kitsukawa

Takesada Akiba

William R McKee

Jeffrey E Koelling

Hiroshi Otori

Jeffrey A McKee

Jing-Shing Shu

Michael P Keleher

Robert N Rountree

A method and apparatus for providing a meshed power and signal bus system on an array type integrated circuit that minimizes the size of the circuit. In a departure from the art, through-holes for the mesh system are placed in the cell array, as well as the peripheral circuits. The power and signal buses of the mesh system run in both vertical and horizontal directions across the array such that all the vertical buses lie in one metal layer, and all the horizontal buses lie in another metal layer. The buses of one layer are connected to the appropriate bus(es) of the other layer using through-holes located in the array. Once connected, the buses extend to the appropriate sense amplifier drivers. The method and apparatus are facilitated by an improved subdecoder circuit implementing a hierarchical word line structure.

System with meshed power and signal buses on cell array

A mask ( ) includes a pattern ( ) having a plurality of substantially rectangular shapes ( ) arranged longitudinally in each of a plurality of substantially parallel rows ( ). The rows ( ) are evenly spaced apart from each other. The substantially rectangular shapes ( ) in each row ( ) are evenly spaced apart from each other and offset from the substantially rectangular shapes ( ) in neighboring rows ( ). The substantially rectangular shapes ( ) define a plurality of T-shapes ( ) connected to and offset from each other.

Mask and method for forming dynamic random access memory (DRAM) contacts

A mask (,) includes a pattern (,) having a plurality of substantially rectangular shapes (,) arranged longitudinally in each of a plurality of substantially parallel rows (,). The rows (,) are evenly spaced apart from each other. The substantially rectangular shapes (,) in each row (,) are evenly spaced apart from each other and offset from the substantially rectangular shapes (,) in neighboring rows (,). The substantially rectangular shapes (,) define a plurality of T-shapes (,) connected to and offset from each other.

An input protection circuit for an MOS device uses a thick-oxide transistor connected as a diode between a metal bonding pad and ground. The channel width of this transistor is chosen to be sufficient to withstand large, short-duration current spikes caused by electrostatic discharge. More important, the spacing between a metal-to-silicon contact to the drain of this transistor and the channel of the transistor (where heat is generated), is chosen to be much larger than usual so the metal of the contact will not be melted by heat propagating along the silicon surface during the current spike due to ESD. This spacing feature also applies to circuits for output pads, or circuits using diode protection devices.

Semiconductor device with electrostatic discharge protection

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Richardson, TX, United States of America

Troy H Herndon