International Business Machines Corporation

International Business Corporation

Troy David Armstrong

William Joseph Armstrong

Naresh Nayar

Curtis Shannon Eide

Gregory Michael Nordstrom

Kenneth Charles Vossen

Gary Ross Ricard

Kyle Alan Lucke

Stuart Zachary Jacobs

Peter Joseph Heyrman

Wade Byron Ouren

Michael Steven Faunce

Jeffrey Jay Scheel

David Anthony Larson Stanton

Adam J McPadden

Thomas R Sand

Michael Joseph Corrigan

Kurt Walter Pinnow

Adam Charles Lange-Pearson

Abdo Esmail Abdo

Tracy James Bashore

Christopher Patrick Abbey

Jeffery David Haumont

James Lee Naylor

Stephanie Maria Forsman

Joseph Thomas Writz

Thomas Richard Crowley

Kenneth Gerald Linn

Andy Wottreng

Erik Tkal

Christopher Brian Wallis

Gergory Michael Nordstrom

George F Eckman

A computer system implements a memory unit, which includes first DRAM devices, second DRAM devices, a first memory controller, and a second memory controller. Each of the first DRAM devices have a first individual memory capacity and each of the second DRAM devices have a second individual memory capacity. The first memory controller is in signal communication with the first DRAM devices and the second memory controller is in signal communication with the second DRAM devices. Each of the first DRAM devices and the second DRAM devices are selectively operable as one of an active DRAM device to stare application data or a spare DRAM device reserved to receive the application data from the active DRAM devices to dynamically over-provision a total memory defined by a sum of the first and second individual memory capacities.

System wide memory technology over-provisioning

A throttling engine throttles access to a high latency hybrid memory. A request is received for partition mapping of a virtual address for an R/W memory page. An entry is added to a partition page table that maps a virtual address to a physical address and comprises access information that is R/W. A throttled flag is set in an entry of a partition page extension table. The throttle entry corresponds to the entry. The access information is saved in an original access part of the partition page extension table, and the access information is replaced with an R value. Upon application fault receipt, a throttling test is performed on an address of the application fault. If the throttling test is false, the fault is passed through to an operating system fault handler and the throttling fault stage is ended, otherwise, a delay is implemented for slowing access to the memory.

Throttling access to high latency hybrid memory DIMMs

Within a hashed page table maintained by a hypervisor, a special host real address configured to access a hardware device using access data intended to be invalidated is identified as part of a firmware assisted dump process for a virtual machine executing on the hypervisor. The special host real address is translated to a corresponding special guest real address. Within the hashed page table, the special host real address is replaced with the corresponding special guest real address, and the corresponding special guest real address is marked as invalid and requiring special handling. Subsequent to the replacing, the special host real address is invalidated. The special guest real address and translated address information are provided to the virtual machine subsequent to the invalidating, the translated address information comprising a set of host real addresses translated to corresponding guest real addresses.

Preserving transient address translation information across a firmware assisted dump procedure

A computer-implemented method and system for affinity based optimization of persistent memory volumes. Responsive to receiving a request for a parent virtual PMEM device, a total memory capacity is apportioned amongst virtual persistent memory (PMEM) resources and physical memory resources. In accordance with a target affinity characteristic, a set of virtual central processor unit (CPU) sockets are assigned. Each virtual CPU socket is configured based on at least one physical central processor unit (CPU) core in conjunction with a subset of the virtual PMEM and physical memory resources. Child virtual PMEM devices are created for respective ones of the virtual CPU sockets, each of the child virtual PMEM devices being dedicated to the parent virtual PMEM device.

Affinity based optimization of virtual persistent memory volumes

Exemplary methods, systems, and products are described for executing an overall quantity of data processing within an overall processing period that include executing repeatedly through a series of iterations a portion of the overall quantity of data processing that can be completed in a set processing period, wherein each iteration includes the set processing period and a variable delay period and calculating the variable delay period for an iteration in dependence upon the set processing period, a portion of the overall quantity of data processing performed during the set processing period of the iteration, the overall quantity of data processing, and the overall processing period.

Executing an overall quantity of data processing within an overall processing period

A resource and partition manager of the preferred embodiments includes a lock mechanism that operates on a plurality of locks that control access to individual I/O slots. The resource and partition manager uses the lock mechanism to obtain a lock on an I/O slot when transferring control of the I/O slot to a logical partition that is powering on and when removing the I/O slot from a logical partition that is powering off. The resource and partition manager uses the lock mechanism to remove control of an I/O slot from, or return control to, an operating logical partition in order to facilitate hardware service operations on that I/O slot or on the physical enclosure in which it is contained.

Controlling resource transfers in a logically partitioned computer system

An apparatus, program product and method of processing access requests for a direct access storage device utilize a 'fair elevator' algorithm to schedule access requests from a plurality of requesters desiring access to a direct access storage device (DASD). In particular, a fair elevator algorithm arbitrates requests by taking into account both the requesters with which various requests are associated, as well as the relative positions of the data to be accessed on the DASD. By sorting access requests based upon both requester identity and DASD position, both multitasking performance and DASD throughput are improved in a balanced manner, thus improving overall system performance.

Fair elevator scheduling algorithm for direct access storage device

A partition manager includes a resource detection mechanism that uses a persistent resource database to determine which resources were seen previously, and to determine which resources are required for a logical partition to start. Once all required resources for a logical partition are detected, the logical partition is started. In this manner, a logical partition may be started as soon as all of its resources are available, without waiting on the resources of other logical partitions. In addition, a missing required resource will prevent a logical partition from starting, thus avoiding the crash of a logical partition due to missing resources.

Apparatus and method for autonomically detecting resources in a logically partitioned computer system

A resource and partition manager of the preferred embodiments includes a lock mechanism that operates on a plurality of locks that control access to individual PCI adaptor slots. The resource and partition manager uses the lock mechanism to obtain a lock on an PCI adaptor slot when transferring control of the PCI adaptor slot to a logical partition that is powering on and when removing the PCI adaptor from a logical partition that is powering off. The resource and partition manager uses the lock mechanism to remove control of an PCI adaptor slot from, or return control to, an operating logical partition in order to facilitate hardware service operations on that PCI adaptor slot or on the physical enclosure in which it is contained.

Controlling resource transfers using locks in a logically partitioned computer system

Methods, systems, and media for timed power-on in a logically partitioned environment are disclosed. Embodiments may disclose determining a time period based upon a time to launch a partition and a time of day associated with the next partition to launch. After determining the time period, a timer is set to boot the system based upon the time period. More specifically, embodiments allow the timed power-on (TPO) and time of day (TOD) of logical partitions to be modified by clients independently of other partitions by determining the system TPO based upon TPOs and TODs of logical partitions as well as the TOD of the system. Some embodiments include initiating a transaction like an interrupt in response to a change in a TPO or TOD of logical partition or the system. Several of such embodiments incorporate adjusting or re-calculating the system TPO in response to the transaction.

Method for scheduling launch a computer system based upon a time of timed power-on partition of logical partitions

An apparatus, program product and method for managing a number of physical connections to a peripheral device. A multipath driver provides a logical connection interface to a client. This interface allows the client to efficiently access the peripheral device over one or more of the physical connections. In so doing, the logical connection interface associates connections with a primary connection, deletes inactive connections from memory, as well as updates and uses a list of active connections to seamlessly route data to the peripheral device.

Multiple connection management system

A logical partition debugger allows debugging one logical partition in a computer system without requiring the shutdown of other logical partitions. The logical partition debugger is implemented in software in the partition manager. The logical partition debugger provides many common debug functions known in existing hardware and software debuggers, but does so in a manner that only the partition being debugged is affected.

Apparatus and method for debugging a logical partition

A resource and partition manager includes a power on/power off mechanism that is used to assure a hardware resource is powered down when control of the resource is removed from a logical partition, and to assure the hardware resource is powered up when control of the hardware resource is transferred to a logical partition. In the alternative, the resource and partition manager may simply place the hardware resource in a power on reset state when the hardware resource is transferred to a logical partition. In this manner, when made available to a partition, the hardware resource is in a power-on reset state, which is the state typically expected by the logical partition.

Apparatus and method for controlling resource transfers in a logically partitioned computer system by placing a resource in a power on reset state when transferring the resource to a logical partition

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Rochester, MN, United States of America

Troy David Armstrong