Texas Instruments Corporation

Troy A Yocum

Mona M Eissa

Freidoon Mehrad

Gregory Boyd Shinn

Joe G Tran

Shawn T Walsh

Michelle L Hartsell

Ju-Ai Ruan

James B Friedmann

Wayne A Bather

Juanita DeLoach

Brian M Trentman

Jaideep Mavoori

Somit Joshi

John E Campbell

Michael J McGranaghan

Janice D Makos

Arun Sivasothy

The invention describes a method for the selective dry etching of tantalum and tantalum nitride films. Tantalum nitride layers () are often used in semiconductor manufacturing. The semiconductor substrate is exposed to a reducing plasma chemistry which passivates any exposed copper (). The tantalum or tantalum nitride films are selectively removed using an oxidizing plasma chemistry.

Selective dry etching of tantalum and tantalum nitride

The invention describes a method for the selective dry etching of tantalum and tantalum nitride films. Tantalum nitride layers () are often used in semiconductor manufacturing. The semiconductor substrate is exposed to a reducing plasma chemistry which passivates any exposed copper (). The tantalum nitride films are selectively removed using an oxidizing plasma chemistry.

In one embodiment, a method for forming a semiconductor structure in manufacturing a semiconductor device includes providing a pad layer on a surface of a substrate, providing a nitride layer on the pad layer, and providing a sacrificial oxide layer on the nitride layer. In a first etching step, at least the sacrificial oxide and nitride layers are etched to define opposing substantially vertical surfaces of at least the sacrificial oxide and nitride layers. In a second etching step, the nitride layer is etched such that the opposing substantially vertical surfaces of the nitride layer are recessed from the opposing substantially vertical surfaces of the sacrificial oxide layer, the sacrificial oxide layer substantially preventing the nitride layer from decreasing in thickness as a result of the etching of the nitride layer. In a third etching step, the substrate is etched to form a trench extending into the substrate for purposes of defining one or more isolation regions adjacent the trench.

Forming a trench to define one or more isolation regions in a semiconductor structure

A method for forming planar isolation structures for integrated circuits. A etch barrier is formed over the isolation fill material and an etch back is performed to remove material above unetched portions of the substrate. The exposed fill material is etched and planarized to form a planar isolation structure.

Shallow trench isolation planarization using self aligned isotropic etch

A post-etch clean up process for OSG. After the trench ( )/via ( ) etch in a dual damascene process, a wet chemistry comprising HF and H O is used to remove residues without etching or damaging the OSG film in the ILD ( ) or IMD ( ).

Wet clean of organic silicate glass films

A post laser blown fuse slag etch for a copper fuse (,) with a barrier metal liner (,), (e.g., Ta,N,, Ta, Ti, Ti,N,). After the fuse (,) is blown, copper and copper complexes may be selectively removed using a nitric acid and H,O,solution. Then, a corrosion inhibitor is used to passivate the surface of exposed copper (,). Next, the barrier metal (,) of slag (,) is removed using a strong basic etch chemistry comprising a base plus H,O,. This solution removes the barrier metal selectively with respect to passivation layer (e.g., silicon nitride) (,) and oxides/FSG (,). A diluted HF solution may then be used to remove any trace metal or oxidized copper.

Post fuse slag etch

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Plano, TX, United States of America

Troy A Yocum