Ati Technologies Inc.

Nxtwave Communications, Inc.

Other

Advanced Micro Devices Corporation

Netwave Communications

Sarnoff Digital Communications

Troy A Schaffer

Christopher H Strolle

Thomas J Endres

Samir N Hulyalkar

Anand M Shah

Raul Alejandro Casas

Binning Chen

Jeffrey S Hamilton

Ravikiran Rajagopal

Stephen L Biracree

Haosong Fu

Feng Huang

Daniel Zhu

Hulyalkar N Samir

Yan Li

A window position optimization for a pilot-aided OFDM system is disclosed. A method of reducing aliasing in an orthogonal frequency division multiplexing (OFDM) system, using window optimization and pilots comprises receiving an RF signal including a pilot, generating a channel frequency response estimate, interpolating the channel estimate to calculate a pilot carrier frequency response, and dynamically selecting a window to capture a channel impulse response to prevent aliasing.

Window position optimization for pilot-aided OFDM system

A TV signal reception system is configured to include adjustable components and a controller to provide instructions to adjust the adjustable components. By pre-arranging configurations corresponding to multiple variants of world wide TV standards, the TV signal reception system may avoid the hardware costs of accomplishing the reception of multiple standards of with parallel hardware for each standard and/or variant.

World wide analog television signal receiver

A robust data extension, added to a standard 8VSB digital television signal, is used to improve the performance of a digital television receiver. Robust data packets are encoded at a 1/3-trellis rate as compared to normal data packets that are encoded at a 2/3-trellis rate. In addition to delivery of robust data for mobile applications, the redundant robust data packets also improve the performance of the receiver in the normal tier of service. In particular, the robust data packets improve the performance of the receiver equalizer filter in the presence of rapidly changing transient channel conditions such as dynamic multipath for both robust data packets and normal data packets. The robust data packets improve the performance of the carrier recovery loop and the symbol timing recovery loop. Backward compatibility with existing receivers is maintained for 1) 8VSB signaling, 2) trellis encoding and decoding, 3) Reed Solomon encoding and decoding, and 4) MPEG compatibility.

Receiver for robust data extension for 8VSB signaling

An AGC circuit includes both wide-band and narrow-band VGAs. Two power monitors monitor the power level of the two VGAs. Based upon the signals provided by the power monitors, the AGC circuit derives two error terms. The AGC circuit filters and combines the error terms to determine a desired adjustment to the total gain and a desired adjustment to the distribution of the gain between the wide-band VGA and the narrow-band VGA. The AGC circuit also minimizes the noise figure of the narrow-band VGA subject to linearity constraints.

Dual loop automatic gain control

An equalizer for use in a communication receiver includes an infinite impulse response (IIR) feedback filter operated in acquisition and tracking feedback modes on a sample by sample basis to form a hybrid Decision Feedback Equalizer (DFE) architecture. In acquisition mode, soft decision samples from the filtered received signal are input to the IIR filter. In the tracking mode, hard decision samples from a slicer are input to the IIR filter. Acquisition and tracking operating modes are selected in accordance with a set of decision rules on a sample by sample basis based on the quality of the current hard decision. If the current hard decision is low quality, then the soft decision sample (acquisition mode) is used. If the current hard decision is high quality, then the hard decision sample (tracking mode) is used. In such manner, the DFE is operated in a hybrid mode, i.e., using both soft and hard decisions on a sample by sample basis. Furthermore, the decision rules that are responsive to signal reliability to select acquisition and tracking modes are adaptive.

Hybrid soft and hard decision feedback equalizer

A multiple channel diversity receiver includes joint automatic gain control (AGC) signal processing wherein the first and second channels of the multiple channel diversity receiver share at least one joint AGC loop. The maximum difference between the AGC feedback signal in the control loop for the first channel and the AGC feedback control signal in the control loop for the second channel is limited to a selectable maximum differential. The AGC control loop with the stronger first RF signal thus limits the maximum amount that the weaker signal is amplified in the AGC control loop with the weaker second RF signal. By limiting the AGC feedback signal in the control loop of the second channel to a maximum differential with respect to the AGC feedback signal in the control loop of the first channel, the weaker signal is not overly amplified thereby avoiding the undue amplification of noise in the second channel.

Diversity receiver with joint automatic gain control signal processing

Original RF carriers are recovered for first and second channels in a diversity receiver and used to de-rotate (demodulate) each of the first and second received signals. The pilot loop filters of each channel are cross coupled to create a joint pilot loop between both channels. The channel with the stronger signal provides a dominant influence on the frequency of the synthesized recovered RF carrier in the channel with the weaker signal. The phase locked pilot loops in both channels will tend to be frequency locked to the frequency of the stronger signal, leaving the respective phase locked pilot loops to make an individual phase adjustment for each channel.

Diversity receiver with joint phase locked loop filter

First and second RF signals in the respective first and second channels of a multiple channel diversity receiver are processed jointly in a joint timing loop filter for baud clock recovery. The channel with the stronger signal determines the frequency of the baud clock for the channel with the weaker signal, leaving the respective PLL's to make individual phase adjustments for each channel. The first and second channels also share a skew corrector for baud clock recovery when the multipath delay between the first and second RF signals is greater than one whole baud clock period. The whole baud skew corrector computes the correlation between the first and second received signals, and if the correlation is low, shifts the first and second signals by one whole baud and recomputes the correlation. The process of shifting the first and second received signals and computing the correlation function is repeated for various whole baud shifts in accordance with a search strategy to find the best (highest) correlation.

Diversity receiver with joint baud clock recovery

A slicer for a decision feedback error equalizer system that processes trellis encoded data using the ATSC trellis code is implemented in two parts. A first part includes a trellis decoder that estimates a single bit of the symbol. The second part includes two partial trellis decoders. A multiplexer directs the received digital samples to one of the two trellis decoders responsive to the estimated symbol. An alternative slicer estimates two bits of the output symbols and selects from among four decoders to fully decode the symbols. The slicer is used in an equalizer having adaptive filters that may operate either on passband or baseband signals. The slicer is used both to recover the carrier signal on which the symbols are modulated and to provide symbols to the second filter that are used to determine filter coefficients for the second filter.

Data slicer for combined trellis decoding and equalization

A digital communication receiver includes a blind equalizer using the Constant Modulus Algorithm (CMA) to compensate for channel transmission distortion in digital communication systems. Improved CMA performance is obtained by using a partial trellis decoder to predict 1 bit or 2 bits of the corresponding 3-bit transmitted symbol. The predicted bits from the partial trellis decoder are used to reduce the effective number of symbols in the source alphabet, which reduces steady state jitter of the CMA algorithm. Specifically, the received input signal to the CMA error calculation is shifted up or down by a computed delta (&Dgr;), in accordance with the predicted bit(s). In addition, a different constant gamma (&ggr;), for the CMA error calculation is selected in accordance with the predicted bit(s). The disclosed technique is applicable to trellis and non-trellis codes in which at least one bit of the present symbol can be predicted in advance and used to reduce the effective number of symbols in the source alphabet.

Equalizer method and apparatus using constant modulus algorithm blind equalization and partial decoding

A diversity receiver is coupled to a composite antenna having first and second antennas physically configured to provide one or more forms of diversity reception. The multiple channel diversity receiver includes first and second RF channels with joint signal processing. First and second RF signals are processed jointly in the multiple channel diversity receiver with respect to tuning, automatic gain control (AGC), baud clock recovery, RF carrier recovery and forward equalization. The multiple channels of the diversity receiver are linked or cross coupled to each other through respective joint processing circuitry. In particular, first and second RF tuners share a common local oscillator and a common AGC feedback loop. First and second front ends share a common baud timing loop and a common pilot carrier recovery loop. Finally, first and second diversity receiver channels share a common sparse equalization filter. By processing first and second signals jointly in the diversity receiver, the receiver provides equal or superior performance to a single receiver processing only the best signal.

Diversity receiver with joint signal processing

A transmission channel equalizer system may be used to process either signals that have been modulated according to quadrature amplitude modulation (QAM) or vestigial sideband modulation (VSB) to convey digital symbols. The equalizer system includes a sparse digital filter having coefficients which are adaptively updated. The filter system includes a finite impulse response (FIR) filter which processes modulated pass-band RF signals and an infinite impulse response (IIR) filter which processes demodulated base-band signals. At least one of the FIR and IIR filters is implemented as a sparse filter. The filter system is responsive to a control signal to switch between processing QAM and VSB signals. The update algorithm for the equalizer employs a constant modulus algorithm (CMA) to acquire the digital signal and a decision directed (DD) algorithm to track the digital signal. The CMA algorithm used when VSB signals are processed is a single axis CMA (SACMA) algorithm. The filter converts the VSB signal into a pseudo QAM signal before the slicing operation which recovers the symbols from the converted VSB signal. The slicer identifies an encoded VSB symbol by partial trellis decoding and quantization from a reduced-set constellation.

Reduced complexity equalizer for multi mode signaling

An adaptive equalizer for use in blind equalization systems to compensate for transmission channel distortion and noise in a digital communication system uses multiple quantization levels for implementation of the Constant Modulus Algorithm (CMA). Different quantization levels are used in different regions of the CMA error function for both passband and baseband equalizers. In one embodiment, a quantizer with a step rise having logarithmic scale is used to digitize the CMA error function. In particular, a quantizer with a step rise in which each level of the quantizer step rise is a power of 2 is used to digitize the CMA error function. In another embodiment, a quantizer with a step rise in which each level of the quantizer step rise is the sum of two or more logarithmic scales is used to digitize the CMA error function. In particular, a quantizer with a step rise wherein each level of the quantizer step rise is the sum of two or more numbers each of which is a power of 2 is used to digitize the CMA error function. The use of logarithmic scales, the sum of logarithmic scales, powers of 2, or the sum of powers of 2 for the quantizer step rise size to digitize the CMA error function make efficient use of shift and add operations to achieve multiplication in the adaptation process.

Adaptive equalizer with enhanced error quantization

An adaptive equalizer for use in blind equalization systems to compensate for transmission channel distortion and noise in a digital communication system quantizes the input signal samples to generate a quantized implementation of the Constant Modulus Algorithm (CMA). To quantize the input signal samples, a nearest-element decision device (a slicer), that is typically present in a digital receiver, is used to pre-compute the quantized CMA error function. The number of unique values for the CMA error term is thereby reduced, and the reduced number of CMA error term values are stored in a lookup table. By greatly reducing the number of received signal values used in the CMA error calculation a relatively small lookup table can be used to compute the CMA error function. Passband implementation is accommodated by incorporating the signal de-rotation factor into the lookup table entries. In one embodiment the CMA multiply operation is replaced with shifts and adders. To make efficient use of shift and add operations to achieve multiplication in the adaptation process, the lookup table values are selected to be either a power of 2 or a minimal sum of powers of 2.

Adaptive equalizer with decision directed constant modulus algorithm

A slicer for a decision feedback error equalizer system which processes trellis encoded data using the ATSC trellis code is implemented in two parts. A first part includes a single-stage trellis decoder which estimates the value of a single bit of the symbol. The second part includes two trellis decoders each of which estimates the values of respective subsets of the symbols in the alphabet given that the single bit is zero or one. A multiplexer is responsive to the single stage trellis decoder to direct the received digital samples to one of the two trellis decoders in the second part of the slicer. An alternative slicer includes a first part which estimates two bits of the output symbols and selects from among four decoders in the second part in order to fully decode the symbols. The smart slicer can be generalized for any set-partitioned code with or without a feedback convolutional code.

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Langhorne, PA, United States of America

Troy A Schaffer