Micron Technology Incorporated

Round Rock Research, LLC

Other

Micron Semiconductor, Inc.

Advanced Memory International, Inc.

Troy A Manning

Brent Keeth

Chris G Martin

Todd A Merritt

Brian L Johnson

Troy D Larsen

Martin L Culley

Richard Cameron Murphy

Glen Earl Hush

Kyle B Wheeler

Timothy P Finkbeiner

Paul S Zagar

Joo S Choi

Brett L Williams

Manny K Ma

Shubneesh Batra

Kevin J Ryan

Dean A Klein

Timothy B Cowles

Jeffery W Janzen

Terry R Lee

Michael B Ball

Paul A LaBerge

Joe M Jeddeloh

Jason T Zawodny

Jim Rehmeyer

Charles H Dennison

Stephen L Casper

Brian M Shirley

Perry Victor Lea

James Brian Johnson

Jonathan D Harms

Brian L Brown

Jeffrey W Janzen

Ming-Bo Liu

Christopher B Cooper

Salman Akram

Sampath K Ratnam

Adrian E Ong

Eugene H Cloud

David K Ovard

George Edward Pax

Roy Edgar Greeff

Ronnie M Harrison

Doyle W Rivers

Michael D Chaine

Dragos Dimitriu

Ebrahim H Hargan

Russel J Baker

J Wayne Thompson

Greg King

Eric J Smith

Adrian H Ong

Dean C Eyres

Ken Waller

Jeffrey L Meader

Steve G Bard

Peter B Gillingham

Donald M Morgan

David V James

Cormac Michael O'Connell

Bruce Millar

Thomas W Voshell

Yoshikazu Morooka

Wallace E Fister

Kim M Pierce

Henry Stracovsky

Desi Rhoden

Donald N North

Perry V Lea

Hans A Wiggers

Mike Pearson

Brett L Wiliams

David B Gustavson

William R Bachand

Glen E Hush

Larsen Troy

Jean Crepeau

The present disclosure includes apparatuses and methods for parallel writing to multiple memory device locations. An example apparatus comprises a memory device. The memory device includes an array of memory cells and sensing circuitry coupled to the array. The sensing circuitry includes a sense amplifier and a compute component configured to implement logical operations. A memory controller in the memory device is configured to receive a block of resolved instructions and/or constant data from the host. The memory controller is configured to write the resolved instructions and/or constant data in parallel to a plurality of locations the memory device.

Apparatuses and methods for parallel writing to multiple memory device structures

Examples of the present disclosure provide apparatuses and methods related to generating and executing a control flow. An example apparatus can include a first device configured to generate control flow instructions, and a second device including an array of memory cells, an execution unit to execute the control flow instructions, and a controller configured to control an execution of the control flow instructions on data stored in the array.

Generating and executing a control flow

The present disclosure includes apparatuses and methods for bank to bank data transfer. An example apparatus includes a plurality of banks of memory cells, an internal bus configured to transfer data between the plurality of banks and an external bus interface, and a bank-to-bank transfer bus configured to transfer data between the plurality of banks.

Bank to bank data transfer

The present disclosure includes apparatuses and methods related to logical operations using memory cells. An example apparatus comprises a first memory cell controlled to invert a data value stored therein and a second memory cell controlled to invert a data value stored therein. The apparatus may further include a controller coupled to the first memory cell and the second memory cell. The controller may be configured to cause performance of a logical operation between the data value stored in the first memory cell and the data value stored in the second memory cell.

Logical operations using memory cells

The present disclosure includes apparatuses and methods related to performing logical operations using sensing circuitry. An example apparatus comprises an array of memory cells and sensing circuitry comprising a primary latch coupled to a sense line of the array. The sensing circuitry can be configured to perform a first operation phase of a logical operation by sensing a memory cell coupled to the sense line, perform a number of intermediate operation phases of the logical operation by sensing a respective number of different memory cells coupled to the sense line, and accumulate a result of the first operation phase and the number of intermediate operation phases in a secondary latch coupled to the primary latch without performing a sense line address access.

Apparatuses and methods for performing logical operations using sensing circuitry

One example of the present disclosure includes performing a comparison operation in memory using a logical representation of a first value stored in a first portion of a number of memory cells coupled to a sense line of a memory array and a logical representation of a second value stored in a second portion of the number of memory cells coupled to the sense line of the memory array. The comparison operation compares the first value to the second value, and the method can include storing a logical representation of a result of the comparison operation in a third portion of the number of memory cells coupled to the sense line of the memory array.

Comparison operations in memory

Methods, systems, and devices for operational code storage for an on-die microprocessor are described. A microprocessor may be formed on-die with a memory array. Operating code for the microprocessor may be stored in the memory array, possibly along with other data (e.g., tracking or statistical data) used or generated by the on-die microprocessor. A wear leveling algorithm may result in some number of rows within the memory array not being used to store user data at any given time, and these rows may be used to store the operating code and possibly other data for the on-die microprocessor. The on-die microprocessor may boot and run based on the operating code stored in memory array.

Operational code storage for an on-die microprocessor

Methods and devices related to transferring data between DRAM and SRAM. One method includes activating a first portion of a dynamic random access memory (DRAM), reading data from the first portion of the DRAM, latching the data from the first portion of the DRAM in one or more sense amplifiers, and writing the data from the one or more sense amplifiers to a first portion of a static random access memory (SRAM).

Transferring data between DRAM and SRAM

The present disclosure includes apparatuses and methods related to performing logical operations using sensing circuitry. An example apparatus comprises an array of memory cells and sensing circuitry coupled to the array. The sensing circuitry is configured to perform a logical operation using a data value stored in a first memory cell coupled to a sense line as a first input and a data value stored in a second memory cell coupled to the sense line as a second input. The sensing circuitry is configured to perform the logical operation without transferring data via a sense line address access.

Methods, systems, and devices for modifiable repair solutions for a memory array are described to support storing repair information for a memory array within the memory array itself. A memory device may include the memory array and an on-die microprocessor, where the microprocessor may retrieve the repair information from the memory array and write the repair information to repair circuitry used for identifying defective memory addresses. The microprocessor may support techniques for identifying additional defects and updating the repair information during operation of the memory array. For example, the microprocessor may identify additional defects based on errors associated with one or more memory cells of the memory array or based on testing performed on one or more memory cells of the memory array. In some cases, a host device may identify additional defects and may notify the microprocessor of the additional defects.

Modifiable repair solutions for a memory array

Growing community of inventors

Meridian, ID, United States of America

Troy A Manning