International Business Machines Corporation

Freescale Semiconductor,inc.

Trong D Nguyen

Nandor G Thoma

Dzung T Tran

Samaksh Sinha

Humberto Felipe Casal

Nitin Pant

Mark L Shulman

Rafey Mahmud

Dual-voltage detectors and related methods are disclosed that receive control signals from a first supply voltage domain and provide multiple disable outputs within a separate supply voltage domain. The disclosed embodiments detect a power supply status in one supply voltage domain (e.g., 1.2 volts, ground) and then assert low voltage disable or reset signals to downstream circuitry within a different supply voltage domain that is powered with different supply voltages (e.g., 1.8 volts, 0.9 volts, ground). In certain embodiments, the dual-voltage detectors provide two disable signals to stacked output drivers that are used to tri-state the stacked output drivers to place them in a high-impedance (HIGH-Z) state, for example, during power-up or power-down operations.

Dual-voltage detector having disable outputs within separate voltage domain and related methods

A buffer and control circuit for a synchronous memory controller includes first and second differential comparators and control logic. The first differential comparator is provided with positive and negative differential input signals and the second differential comparator is provided with offset positive and negative differential input signals. The first and second differential comparators generate output signals based on magnitudes of the positive and negative differential input signals and the offset positive and negative differential input signals. The control logic generates a reference strobe signal based on the output signals.

Buffer and control circuit for synchronous memory controller

A signal delay device is provided which enhances noise immunity by using a differential circuit, but also maintains the phase of the input clock signals. This device will also correct the phase of clock signals which are input to the delay device in an out of phase condition. The present invention is a delay circuit that includes functionally connecting each of the output signals with each of the input signals. Thus, the output signals are dependent on the same input and the steady state condition is the point where the leading edge of a first output signal intersects the trailing edge of a second output signal at the point which corresponds to one half of the pulse height of both signals. Since the signals are complements of one another, they will cross at 50% of their pulse height when they are 'in phase'. Thus, the present invention will maintain 'in phase' input signals and seek an 'in phase' condition for signals that are input to the delay circuit which are 'out of phase'.

Differential delay line circuit for outputting signal with equal pulse

A dynamically switchable clock system having a symmetrical output signal includes a frequency doubler which couples the input frequency to provide greater resolution and synchronization of an output signal to an input signal in the frequency divider and the facility to handle odd divides as even divides at double frequency, a counter controlled by a divisor select signal, first and second compare circuits which compare against the preprogrammed count for division, the compare circuits receiving an input from the divisor select circuits, and having outputs to a counter reset line and to an output clock S/R latch which provides the frequency divided symmetrical output signal.

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Austin, TX, United States of America

Trong D Nguyen