Synopsys, Inc.

Trinanjan Chatterjee

Brent L Gregory

Jing Chyuarn Lin

Paul Il Estrada

Emil F Girczyc

Srinivas Raghvendra

Andrew Seawright

This invention provides a method for displaying circuit analysis results corresponding to parts of the circuit near the portion of the hardware description language (HDL) specification that generated that part of the circuit. The invention also includes a method for using probe statements in the HDL specification to mark additional points in the initial circuit that should not be eliminated during optimization. This improves the ability to display circuit analysis results near the appropriate part of the HDL specification.

Architecture and methods for a hardware description language source

A digital circuit is synthesized from a text description of a digital system. During synthesis, a parse tree with parse nodes is constructed and retained. The relationship between the parse nodes and the circuit elements synthesized from those parse nodes is retained. Using that relationship, analysis results associated with circuit elements can be related to the text that generated those circuit elements. In particular, the analysis results can be used to set the display characteristics, such as font or size, of the text associated with those results.

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Sunnyvale, CA, United States of America

Trinanjan Chatterjee