Ncr Corporation

Tri T Vo

Rocky M Young

A method and apparatus of bridging a first device with a second device operating at a different clock frequency is described. The apparatus comprises a first bus slave interface coupled to the first device, and a second bus master interface coupled to the first bus slave interface and the second device, a second bus slave interface coupled to the second device, and a first bus master interface coupled to the second bus slave interface and the first device.

Asynchronous PCI-to-PCI Bridge

Apparatus for correcting the byte alignment of multiple-byte data words during DMA word transfers. The apparatus includes a four-byte input word bus and a four-byte output word bus. A carrier register stores the second, third and fourth bytes of a first four-byte data word received on the input bus. A data selector including four 4:1 multiplexers determines which of the three stored word bytes and which of four bytes corresponding to a second data word received on the input bus should be placed on the four-byte output word bus and the sequential order of the bytes on the bus.

Pipe-line method and apparatus for byte alignment of data words during

A circuit for the stable synchronization of an asynchronous data signal. The circuit comprises a first latch for receiving a first asynchronous data signal, a first delayed system clock signal, and a synchronized reset signal and for providing a system clock synchronized version of the first asynchronous data signal. A first delaying circuit receives a system clock signal and the first asynchronous data signal and provides the first delayed system clock signal. The circuit also includes a second latch for receiving a second asynchronous data signal which is a function of the inverse of the first asynchronous data signal and a second delayed system clock signal, and for providing the synchronized reset signal. A second delaying circuit receives the system clock signal and the first asynchronous data signal and provide the second delayed system clock signal.

Circuit for stable synchronization of asynchronous data

A system is disclosed which reduces the cycle time required for performing virtual look-ahead memory operations in computer systems employing random access memory and paging. In a preferred embodiment of the invention, a processor (CPU) outputs a desired virtual address to an address translation unit (ATU) and to a memory output control unit (MOC) and also outputs processor signals to the ATU and to a memory state generator (MSG). The virtual address is comprised of a first real address and a second virtual address. During a first cycle this first real address is gated through a memory output control unit (MOC) to cause an addressable memory, which is arranged to store data in a page format, to commence memory addressing prior to the completion of translation by the ATU. During the first cycle the ATU translates the second virtual address into second and third real address portions. During a second cycle a decoder decodes the third real address portion to develop memory operation signals which determine which one of a plurality of virtual memory operations is to be performed. The MSG is responsive to these memory operation signals and to the processor signals for developing a set of state signals which determines the type of memory operation that is to be performed, as well as the number of cycles required to perform that operation. Under the control of the set of state signals from the MSG, a memory timing control circuit (MTC) controls the MOC to develop memory control signals and to gate the second real address from the ATU and the memory control signals to the addressable memory to access the data in a reduced cycle time for the desired virtual memory operation. The system has the capability of also performing a plurality of real memory operations.

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San Diego, CA, United States of America

Tri T Vo