University of Michigan

Arm Limited

Environmental Research Institute of Michigan

Trevor N Mudge

David Theodore Blaauw

Krisztian Flautner

Todd Austin

Dennis Sylvester

David Michael Bull

Sudhir Kumar Satpathy

Ronald George Dreslinski, Jr

Sandunmalee Nilmini Abeyratne

David Andrew Roberts

Ganesh Suryanarayan Dasika

Robert M Lougheed

Reetuparna Das

Steven M Martin

Supreet Jeloka

Nam S Kim

Joseph Michael Pusdesris

Ronald George Dreslinski

David Walter Flynn

Stuart David Biles

David Alan Fick

Carlos Alfonso Tokunaga

Scott Mahlke

Yiping Kang

Hun Seok Kim

Gregory Kengho Chen

Geoffrey Wyman Blake

Haojie Ye

Yajing Chen

Shengshuo Lu

Thomas Friedric Wenisch

Fu Cheng

Ronald G Dreslinski

Byoungchan Oh

Heewoo Kim

Nishil Talati

Thomas D Manville

Ronald Dreslinski

John Kloosterman

Andrea Pellegrini

Benjamin Allen Vandersloot

Jonathan Beaumont

David Thomas Manville

Davoud Anoushe Jamshidi

Jonathan Bailey

The performance of modern recommendation models is limited because of the memory bandwidth-hungry embedding layer reductions. A novel hybrid memory system is presented with DRAM and RRAM with PIM capability. The performance of traditional RRAM PIM is limited by the latency of bit-serial computation. The hybrid memory system presents a comprehensive optimization approach that includes access-pattern aware mapping, compute complexity reduction, and selective PIM reduction to offset this computation latency. An evaluation shows that the hybrid memory system offers significant performance, energy, and EDP improvement of 2.6×, 1.7×, and 4.4×, on average, compared to a CPU baseline.

DRAM-RRAM hybrid memory system for recommendation models

A technique is provided for processing thread groups, each thread group having associated program code comprising a plurality of regions that each require access to an associated plurality of registers providing operand values for the instructions of that region. Capacity management circuitry is arranged, for a thread group having a region of the associated program code that is ready to be executed, to perform an operand setup process to reserve sufficient storage elements within an operand staging unit to provide the associated plurality of registers, and to cause the operand value for any input register to be preloaded into a reserved storage element allocated for that input register, an input register being a register whose operand value is required before the region can be executed. Scheduling circuitry selects for processing a thread group for which the operand setup process has been performed in respect of the region to be executed.

Dynamically allocating storage elements to provide registers for processing thread groups

An integrated circuit includes one or more portions having error detection and error correction circuits and which is operated with operating parameters giving finite non-zero error rate as well as one or more portions formed and operated to provide a zero error rate.

Error recovery within integrated circuit

Subject matter disclosed herein may relate to arithmetic units of processors, and may relate more particularly to configurable arithmetic units. Configurable arithmetic units may comprise a plurality of basic units, and may further comprise a programmable fabric to selectively connect the plurality of basic units at least in part to process one or more sets of parameters in accordance with one or more specified arithmetic operations.

Configurable arithmetic unit

An interconnect within an integrated circuit provides arbitration to select one of a plurality of signal inputs for connection to a signal output. The arbitration applied uses a first arbitration parameter value, in the form of a time stamp value, and, if two or more signal inputs share such a time stamp value, then uses a second arbitration parameter, in the form of a least recently granted value. The time increment applied to the time stamp value associated with each signal input when it is granted access to the signal output is selected to reflect the quality of service to be associated with that signal input. When a comparison is made between time stamp values, the lowest time stamp value is given priority. A large time increment value corresponds to a low priority (quality of service).

Apparatus and methods for generating a selection signal to perform an arbitration in a single cycle between multiple signal inputs having respective data to send

Various implementations described herein are directed to an integrated circuit. The integrated circuit may include a memory cell configured to operate in multiple retention states including a static retention state and a dynamic retention state. The integrated circuit may include a controller configured to selectively apply different voltage levels to the memory cell based on the retention state of the memory cell.

Enhanced memory device

A data processing apparatus and method for accessing operands stored within a set of registers. Instruction decoder circuitry, responsive to program instructions, generates register access control signals identifying for each program instruction which registers in the register set are to be accessed by the processing circuitry when performing the processing operation specified by that program instruction. The set of registers are logically arranged as a plurality of register groups, with each register in the set being a member of more than one register group. Each program instruction includes a register specifier field, and instruction decoder circuitry is responsive to each program instruction to determine a selected register group, and to determine one or more selected members of that selected register group. The instruction decoder circuitry then outputs register access control signals identifying the register corresponding to each selected member of the selected register group.

Data processing apparatus and method for decoding program instructions in order to generate control signals for processing circuitry of the data processing apparatus

A hardware transactional memoryis provided within a multiprocessorsystem with coherency control and hardware transaction memory control circuitrythat serves to at least partially manage the scheduling of processing transactions in dependence upon conflict data. The conflict data characterizes previously encountered conflicts between processing transactions. The scheduling is performed such that a candidate processing transaction will not be scheduled if the conflict data indicates that one of the already running processing transactions has previously conflicted with the candidate processing transaction.

Contention management for a hardware transactional memory

Single cycle arbitration within an interconnect

A data processing apparatus has a memory rename table for storing memory rename entries each identifying a mapping between a memory address of a location in memory and a mapped register of a plurality of registers. The mapped register is identified by a register number. In response to a store instruction, the store target memory address of the store instruction is mapped to a store destination register and so the data value is stored to the store destination register instead of memory. A memory rename entry is provided in the table to identify the mapping between the store target memory address and store destination target register. In response to a load instruction, if there is a hit in the memory rename table for the load target memory address then the loaded value can be read from the mapped register instead of memory.

Data processing apparatus with memory rename table for mapping memory addresses to registers

A data processing systemis provided with branch prediction circuitryfor performing branch prediction operations. Next branch table circuitrystores data identifying from a given branch instruction what will be the address of the next branch instruction to be encountered within the program flow. This next branch instruction address is supplied to the branch prediction circuitrywhich uses it to form its prediction prior to that next branch instruction being identified as such by the instruction decoder. This permits branch prediction to commence earlier in the branch prediction circuitrythan would otherwise be the case.

Next branch table for use with a branch predictor

Interconnect circuitryhas a plurality of data source circuitsconnected to respective input pathsand a plurality of data destination circuitsconnected to respective output paths. Connection cellsprovide selective connections between input pathsand output paths. Arbitration circuitryprovides adaptive priority arbitration between overlapping requests received at different input paths. Priority bitswithin a matrix of priority bitfor each output pathare used to represent the priority relationships between different input paths which compete for access to that output path. Update operations are applied on a per row or per column basis within the matrix to implement update schemes such as least recently granted, most recently granted, round robin, reversal, swap, selective least recently granted, selective most recently granted etc.

Crossbar circuitry for applying an adaptive priority scheme and method of operation of such crossbar circuitry

Growing community of inventors

Ann Arbor, MI, United States of America

Trevor N Mudge