Sgs-thomson Microelectronics Limited

Stmicroelectronics Gmbh

Inmos Limited

Trevor K Monk

Andrew M Hall

Curtis Dicke

A ring oscillator having an odd number of single ended stages, each stage including two transistors connected as a current mirror. The stage provides for low-voltage performance and improved process tolerance characteristics.

Ring oscillator using current mirror inverter stages

A dividing circuit comprises a plurality (N) of transistor stages connected in a ring. Each stage comprises a first pair of transistors of a first conductivity type connected in series between a first voltage level and an output node, a second pair of transistors of a second conductivity type connected in series between a second voltage level and said output node, wherein control nodes of a first transistor of each said transistor pair are connected together to provide an input node for the stage, and control nodes of a second transistor of each said transistor pair are connected together to provide a clock node for the stage, wherein the input node of each stage is connected to the output node of a preceding stage whereby an output signal is generated at each of said output nodes, each cycle of the output signal representing N cycles of a clock signal applied to said clock nodes of the stages, the output signal having a duty cycle that is closer to 50% than a duty cycle of said clock signal.

Dividing circuit and transistor stage therefor

A programmable dividing circuit comprises a first plurality N of similar transistor stages connected in a divide-by-N sequence, wherein N is an odd integer, the transistor stages being configured so that when an output of the last stage is supplied to a first stage in the sequence, the dividing circuit operates as a divide-by-N circuit in which an output signal is generated which has one cycle for every N cycles of a clock signal applied to the transistor stages. The circuit includes a tri-state inverter selectively connectable in a divide-by-M sequence with a second plurality M of transistor stages, wherein M is an even integer, and wherein the second plurality M of transistor stages includes at least some of said first plurality N of transistor stages, including said first stage, whereby when an output of a last stage in the divide-by-M sequence is supplied to the first stage, the circuit operates as a divide-by-M circuit in which an output signal is generated which has one cycle for every M cycles of a clock signal applied to the transistor stages. The circuit includes a switching circuit having at least two inputs and arranged to selectively connect to the first stage, the output of the last stage in either the divide-by-N sequence or the divide-by-M sequence, whereby the circuit can be programmed to operate as a divide-by-N or divide-by-M circuit.

Programmable divider circuit with a tri-state inverter

A dividing circuit comprises, connected in a ring, a plurality M of transistor stages, where M is an even integer. Each transistor stage comprises an input node, a clock node and an output node. A tri-state inverter stage has an input node connected to the output node of a preceding transistor stage in the ring, an enable node connected to the clock nodes of the transistor stages, and an output node connected to the input node of a subsequent transistor stage in the ring. Each transistor stage comprises a first pair of transistors of a first conductivity type connected in series between a first voltage level and an output node, and a second pair of transistors of a second conductivity type connected in series between a second voltage level and said output node, wherein control nodes of a first transistor of each said transistor pair are connected together to provide the input node for the stage, and control nodes of a second transistor of each said transistor pair are connected together to provide the clock node for the stage, whereby when an input clock signal is applied to the clock nodes of the transistor stages, an output signal is generated at the output node of the tri-state inverter in which each cycle represents M cycles of the input clock signal.

Dividing circuit for dividing by even numbers

An off-chip driver circuit can operate in an output mode to drive a signal supplied at its input terminals to an output terminal. It can also operate in an input mode in which signals are driven from an external circuit via the output terminal onto the chip. In an output mode, the output terminal is clamped to reduce the effect of overshoot voltages, for example as a result of reflections from the external circuits.

Off-chip driver circuit

An off-chip driver circuit having circuitry for providing protection against high voltages when the off-chip driver circuit is disabled is described. The circuitry for providing protection against high voltages utilizes a minimum number of transistors and therefore minimizes the chip area utilized by the off-chip driver circuit. An off-chip driver circuit has an input terminal and an output terminal. A pull-up transistor has a controllable path connected between a first power supply voltage and the output terminal of the off-chip driver circuit, and a control terminal connected to the input terminal via a pass gate connected to isolate the input terminal from high voltages applied to the output terminal. A control transistor has a controllable path connected between the control terminal of the pull-up transistor and the output terminal, and a control terminal connected to a control potential. An auxiliary pass transistor has a control terminal and a controllable path connected between a reference terminal and the control terminal of the pull-up transistor. An auxiliary control transistor has a control terminal connected to receive the control potential, and a controllable path connected between the output terminal and the control terminal of the auxiliary pass transistor. Auxiliary circuitry holds the control terminal of the auxiliary pass transistor in a state determined by the auxiliary control transistor. The auxiliary circuitry may include an auxiliary pull-down transistor having a controllable path connected between the control terminal of the auxiliary pass transistor and a reference potential, and a control terminal connected to a voltage selected to maintain the auxiliary pull-down transistor on.

Frequency Doubler

Low voltage high frequency ring oscillator for controling phase-shifted

A quadrature oscillator is provided constructed of NOR gates in the manner of a non-linear circuit which is inherently unstable and which cycles sequentially through four distinct states at a rate determined by the constitution of the NOR gates. The quadrature oscillator includes first and second stages that each include first and second NOR gates. The output of the first NOR gate of the first stage is connected as an input to the second NOR gate of each of the first and second stages. The output of the second NOR gate of the first stage is connected as an input to the first NOR gate of each of the first and second stages. The output of the first NOR gate of the second stage is connected as an input to the first NOR gate of the first stage and the second NOR gate of the second stage. The output of the second NOR gate of the second stage is connected as and input to the second NOR gate of the first stage and the first NOR gate of the second stage. Each of the NOR gates includes first and second input transistors that each have a control node for receiving an input signal and a controllable path between an output node and a reference voltage, a diode-connected transistor connected between the output node and the reference voltage, and a current source connected to the output node.

Quadrature oscillator having a variable frequency

A switching circuit for an FET transistor includes a controlled current circuit coupled to the gate of the FET. The input to the controlled current circuit represents a desired rate of change of gate voltage of the FET and is generated by a circuit responsive to the average specific transconductance of two FETs of similar specific transconductance operating at different drain circuit densities.

Output noise reduction circuit

A memory is provided with at least one temporary store and write abort circuitry having a control signal store and gating circuitry responsive to an output from the control signal store. Write circuitry loads data and an associated address in the temporary store during one write cycle and transfer circuitry transfers the data to the associated address during a subsequent write cycle when the write operation is not to be aborted. Read circuitry includes a comparator for comparing a read address with an address in the temporary store and transfer circuitry includes selection circuitry to select an output of data either from the temporary store or the memory dependent on the output of the comparator circuitry, an output from the temporary store being prevented if the control signal store indicates that the write operation is to be aborted.

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Chepstow, United Kingdom

Trevor K Monk