Micron Technology Incorporated

Trevor Conrad Meyerowitz

Dhawal Bavishi

Fangfang Zhu

A first command is scheduled on a command bus, where the first command requires use of a data bus resource at a first time period after scheduling the first command. Prior to the first time period, a second command is identified according to a scheduling policy. A determination is made whether scheduling the second command on the command bus will cause a conflict in usage of the at least one data bus resource. In response to determining that scheduling the second command will cause the conflict in usage, a third lower-priority command is identified for which scheduling on the command bus will not cause the conflict in usage. The third command is scheduled on the command bus prior to scheduling the second command, even though it has lower priority than the second command.

Controller command scheduling in a memory system to increase command bus utilization

A system having a processing device and a controller, operatively connected to a memory sub-system via a communication channel, to: store information identifying an amount of available capacity of a buffer of the memory sub-system; transmit, through the communication channel to the memory sub-system, one or more write commands to store data in memory components of the memory sub-system, where the memory sub-system queues the one or more write commands in the buffer; update the information by deducting, from the amount of available capacity, an amount of buffer capacity used by the one or more write commands to generate a current amount of available capacity of the buffer; and determine whether to generate an information request to the memory sub-system based at least in part on the current amount of available capacity.

Optimize information requests to a memory system

A memory system having memory components and a processing device to: receive, from a host system, write commands to store data in the memory components; store the write commands in a buffer; execute at least a portion of the write commands; determine an amount of available capacity of the buffer that becomes available after execution of at least the portion of the write commands; receive, from the host system, a request for information about available capacity of the buffer; and determine whether to transmit a response signal corresponding to the request based at least in part on the amount of available capacity.

Throttle response signals from a memory system

A memory system having memory components and a processing device to receive, from a host system, write commands to store data in the memory components, store the write commands in a buffer, and execute at least a portion of the write commands. For example, this write buffer capacity can be represented by write credit values on the host and the subsystem. The processing device determines an amount of available capacity of the buffer that becomes available after execution of at least the portion of the write commands, and signals the host system to receive information identifying the amount of available capacity, without a pending information request received from the host system.

Proactive return of write credits in a memory system

A processing device identifies a portion of data in a cache memory to be written to a managed unit of a separate memory device and determines, based on respective memory addresses, whether an additional portion of data associated with the managed unit is stored in the cache memory. The processing device further generates a bit mask identifying a first location and a second location in the managed unit, wherein the first location is associated with the portion of data and the second location is associated with the additional portion of data, and performs, based on the bit mask, a read-modify-write operation to write the portion of data to the first location in the managed unit of the separate memory device and the additional portion of data to the second location in the managed unit of the separate memory device.

Bit masking valid sectors for write-back coalescing

A memory system having memory components and a processing device to: receive a write request from a host system; store data of the write request in a portion of a buffer of the memory system during a first time period in which the write request is pending in the memory system; receive a read request from the host system; and store data of the read request in a portion of the buffer during a second time period in which the read request is pending in the memory system. The portion of the buffer storing the data of the write request overlaps at least in part with the portion of the buffer storing the data of the read request.

Buffer management in memory systems for read and write requests

A method comprising identifying a portion of data in a first memory component to be written to a managed unit of a second memory component and determining whether an additional portion of data in the first memory component associated with the managed unit is stored at the cache memory. The method further includes generating a bit mask identifying locations of the managed unit associated with the portion of data and the additional portion of data and performing, based on the bit mask, a write operation comprising the portion of data and the additional portion of data to the managed unit of the second memory component.

A memory system having memory components, and a processing device, operatively coupled with the memory components, to: receive read requests from a host system to retrieve data from the memory components; store the read requests in a buffer; track ages of the read requests and priorities specified by the host system for the read requests; and schedule execution of a first read request from the buffer based on an age of the first read request and a threshold time period.

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Morgan Hill, CA, United States of America

Trevor Conrad Meyerowitz