Cirrus Logic Inc.

Silicon Laboratories Inc.

Trenton John Grale

Yan Zhou

David S Trager

Zhong You

Vitor Pereira

Guner Arslan

Jason Powell Rhode

Karl Ernesto Thompson

Joel W Page

Jeffrey A Tindle

Zhuan Ye

Erng Sing Wee

Sumant Sathe

John B Youngblood

Sijiam Chen

J A Bolton

Die-to-die communication links for receiver integrated circuit dies within multi-die systems and related methods are disclosed for radio frequency (RF) receivers. The disclosed embodiments provide die-to-die communication links that allow for direct communication of operating parameters between receiver integrated circuit dies and other integrated circuit dies within a multi-die system so that the operation of receive path circuitry can be adjusted without requiring intervention from an external host processor integrated circuit. A variety of operating parameter information can be communicated through the die-to-die communication links so that the integrated circuit dies can quickly adjust to changing signal conditions without requiring intervention by the external host processor integrated circuit.

Die-to-die communication links for receiver integrated circuit dies and related methods

Clock signal control circuitry including a selector for selecting between a first clock signal and an inverse of the first clock signal and a phase detector for determining a phase relationship between the first clock signal and the second clock signal and in response causing the selector to select between the first clock signal and the inverse of the first clock signal.

Clock phase detector for noise management

A low power programmable digital filter integrated circuit architecture has a programmable front end servicing up to 4 digital sources. Changing the programming of the front end permits digital outputs from different sensor types to be accommodated. Digital filtering is accomplished using a digital signal processor that is programmable to accommodate different decimation ratios. A serial data output register receives the filtered digital signals and provides them to an output port. The digital filter integrated circuit may be connected in a token passing configuration with other digital filter integrated circuits to increase the number of sources accommodated.

Signal processing integrated circuit

A data converter includes first and second input signal paths receiving an input signal having an input frequency, the first input signal path dividing the input frequency by a first divisor and the second input signal path dividing the input frequency by a second divisor, the second divisor being greater than the first divisor. A selector selects between an output of the first input signal path and an output from the second input signal path in response to a state of a control signal. Control circuitry monitors a selector output signal frequency and a current state of the control signal and selectively resets the state of the control signal to set the selector output frequency to a desired frequency.

Data conversion circuits and methods with input clock signal frequency detection and master mode output clock signal generation

A low power, low area shift register permits control over delay by dividing the shift register cells into a plurality of segments that are serially connected. A first selector provides data from a shift register input selectively to an input of one of the segments. A second selector provides data from an input or output of a selected cell of one segment of shift register cells to a shift register output.

Low-power low-area shift register

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Austin, TX, United States of America

Trenton John Grale