Lattice Semiconductor Corporation

Trent Whitten

Kam Fai So

Ravindar Mohan Lall

Robert M Bartel

Mose Wahlstrom

Michael G France

Glenn Thomas O'Rourke

John Jiang

Systems and methods are provided for generating accurate current ratios from a current mirror including an array of output transistor and a corresponding array of switches. Each switch couples in series with its corresponding output transistor. A control logic circuit controls the switches to cancel mismatches for the output transistors.

Transistor matching for generation of precise current ratios

In one embodiment, a collector current driver is provided that controls the collector current for a bipolar transistor temperature transducer. The collector current driver is configured to use negative feedback to generate an emitter current for the bipolar transistor responsive to target current.

Collector current driver for a bipolar junction transistor temperature transducer

In one example, a method of tuning an oscillator of a phase-locked loop (PLL) circuit includes adjusting a coarse control signal to select one of a plurality of frequency tuning curves of the oscillator. The method includes adjusting a fine control signal to select a position on the selected frequency tuning curve. A frequency of the oscillator is determined by the coarse control signal and the fine control signal. The method includes attempting to detect a lock between a feedback signal and a reference signal. A frequency of the feedback signal is determined by the frequency of the oscillator. The method includes comparing the fine control signal to a reference value if the lock is detected. The method includes adjusting the coarse control signal to select a different one of the frequency tuning curves if the selected position on the selected frequency tuning curve is outside a desired tuning range.

Oscillator tuning for phase-locked loop circuit

In one embodiment of the invention, a programmable logic device includes a plurality of programmable resources; non-volatile configuration memory adapted to store configuration data for configuring the plurality of programmable resources; a register adapted to load configuration data into the non-volatile configuration memory; and test circuitry coupled to the register. The test circuitry is adapted to configure a programmable resource with test data stored in the register rather than with configuration data stored in the non-volatile configuration memory. In another embodiment of the invention, the programmable logic device includes a buffer coupled between the configuration memory and a programmable resource, and the test circuitry includes a logic circuit coupled between the register, the configuration memory, and the buffer. The logic circuit is responsive to a test mode signal to route test data from the register to the buffer.

Programmable logic device and method of testing

A programmable logic device may comprise a plurality of programmable resources and non-volatile configuration memory to store configuration data by which to configure the programmable resources. Test override circuitry may determine a test mode and selectively override the configuration data stored in the non-volatile configuration memory during the test mode for configuring the programmable resources based at least in part on test configuration data other than the configuration data stored in the non-volatile memory. A buffer may be operable to drive a configuration select node for at least one of the programmable resources for designating a configuration therefore based on the configuration data of the non-volatile memory. The test override circuitry may comprise a pull-down circuit operable, when enabled dependent on the test configuration data, to drive the buffer with a high/low level capable of overriding a state of the non-volatile configuration memory.

Methods are described herein, for improving the accuracy of propagation delay measurements of programmable electronic devices in a production environment. In one method, a built-in self-test is implemented by configuring an oscillator and a counter connected to each other within the PLD. The oscillator is enabled to oscillate for a pre-determined length of time and to cause the counter to count up at the end of each cycle of oscillation. The counter reading is correlated to an accurate propagation delay measurement by using a previously generated counter-delay correlation curve. In other methods, the counter is built outside of the logic of the PLD. Methods are described for adapting typical output macro cells to provide combinatorial feedback for configuring oscillators within PLDs without such capabilities.

Measuring propagation delays of programmable logic devices

A CMOS Schmitt Trigger circuit design provides a relatively high speed device having a tight, substantially monotonic hysteresis characteristic which is substantially independent of fabrication process parameters and can be used with relatively wide power supply designs, including operating a relatively low Vcc. Tight trip point variation is maintained in conjunction with process, voltage, and temperature changes. The circuit is adaptable for forming an integrated circuit buffer element.

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Beaverton, OR, United States of America

Trent Whitten