Freescale Semiconductor,inc.

Nxp Usa, Inc.

Trent Uehling

Kevin John Hess

Brett P Wilkerson

Chee Seng Foong

Tingdong Zhou

Tim V Pham

Leo M Higgins, Iii

George R Leal

Scott K Pozder

Ilko Schmadlak

Edward Outlaw Travis, Jr

Burton Jesse Carpenter

Ruiqi Tian

James S Golab

Lakshmi Narayan Ramanathan

Lawrence Scott Klingbeil

David Clegg

Derek S Swanson

Katie C Yu

Sriram Neelakantan

Kelly F Folts

Mostafa Vadipour

A semiconductor device substrate is provided. The substrate includes an embedded trace substrate (ETS) portion. The ETS portion includes a first conductive layer embedded in the ETS portion at a first major surface. A portion of the first conductive layer is patterned to form a signal line. A non-conductive layer is disposed between the first conductive layer and a second conductive layer second embedded in the ETS portion. A third conductive layer is formed over the first major surface of the ETS portion. The third conductive layer is configured to form a stripline with the signal line of the first conductive layer.

Device package substrate structure and method therefor

Embodiments are provided herein for a substrate having one or more embedded traces and a method for fabricating one or more embedded traces. The method includes: forming a bump on a first major surface of a substrate, the bump having a height measured from the first major surface to a top surface of the bump; forming a trace comprising: a lower trace portion that directly contacts the first major surface, a sidewall trace portion that directly contacts at least one sidewall of the bump, and an upper trace portion that directly contacts the top surface of the bump; depositing a blanket dielectric layer over the trace; and etching away a top portion of the blanket dielectric layer to expose a top surface of the upper trace portion.

Method of fabricating embedded traces

Embodiments of a semiconductor packaged device and method of making thereof are provided, the device including a substrate; a first flip chip die mounted to a first major surface of the substrate; a second flip chip die mounted to the first major surface of the substrate, the second flip chip die laterally adjacent to the first flip chip die on the first major surface; and a wire bond formed between a first bond pad on the first flip chip die and a second bond pad on the second flip chip die.

Multiple interconnections between die

Embodiments of a microelectronic packaged device and methods of making are provided, where the microelectronic packaged device includes a system package comprising a first die and a second die, wherein the first die and the second die are laterally positioned to one another, and the first die and the second die are laterally separated from one another by mold compound; and a conductive trace formed between a first conductive surface on an exposed surface of the first die and a second conductive surface on an exposed surface of the second die, wherein the conductive trace is laser sintered directly on the first conductive surface, on a portion of the exposed surface of the first die, on a portion of a top surface of the mold compound, on a portion of the exposed surface of the second die, and on the second conductive surface.

Laser sintered interconnections between die

A method and apparatus are provided for fabricating an electro-optical interconnect on an integrated circuit () in which an optical circuit element () is formed by forming a cylinder-shaped conductive interconnect structure () with one or more conductive layers formed around a central opening () which is located over an optically transparent layer () located over the optical circuit element ().

Copper tube interconnect

A method for manufacturing a semiconductor device is disclosed. The method includes generating a thermo-mechanical stress within a plurality of layers of a wafer, and after generating the thermo-mechanical stress, testing an interfacial strength level associated with one or more of the plurality of layers.

Methods and structures for detecting low strength in an interlayer dielectric structure

The present disclosure provides embodiments for a semiconductor structure including a heat spreader that includes a graphene grid having a first major surface and a second major surface opposite the first major surface. The graphene grid has a plurality of holes, each hole having a first opening in the first major surface and a second opening in the second major surface. The heat spreader also includes a first copper portion covering the first major surface of the graphene grid, a second copper portion covering the second major surface of the graphene grid, and a plurality of copper vias filling the plurality of holes.

Heat spreader and method for forming

By now it should be appreciated that there has been provided methods for making a packaged semiconductor device (and the resultant device) including a via layer that includes a top surface and a bottom surface; a plurality of vias within the via layer, wherein the plurality of vias extend from the bottom surface to the top surface; a first via of the plurality of vias extending from the bottom surface to the top surface at a first angle; and a second via of the plurality of vias extending from the bottom surface to the top surface at a second angle.

Substrate core via structure

A packaged electronic device includes a package substrate, an electronic component die mounted to the package substrate, and an encapsulant bonded to a portion of the package substrate at a catechol group adhesion promoted interface that includes benzene rings bonded with the package substrate and the encapsulant.

Semiconducitive catechol group encapsulant adhesion promoter for a packaged electronic device

A semiconductor structure includes a heat sink. The heat sink having a first major surface, a second major surface, a first sidewall surface, and a through-opening extending from one of the first sidewall surface or the first major surface of the heat sink to the second surface of the heat sink, and wherein the through-opening has an inflow region, a restrictive region, and an outflow region. The restrictive region is located between the inflow region and the outflow region, wherein the inflow region has an inflow surface opening at the one of the first sidewall or the first major surface, and the outflow region has an outflow surface opening at the second major surface. A cross-sectional area of the restrictive region is less than an area of the inflow surface opening and less than an area of the outflow surface opening.

Heat sink having a through-opening

A collapsible probe tower device and methods of forming thereof, are disclosed. In one example embodiment, a method of forming a device includes providing a semiconductor die substrate having a contact pad and a probe pad, wherein the contact pad and probe pad are adhered to the substrate, forming a contact bump by applying a conductive material to a contact structure surface of a contact tower, wherein the contact tower includes the contact pad, forming a probe bump by applying a conductive material to a probe structure surface of a probe tower, wherein the probe tower includes the probe pad, and heating the conductive material that forms the contact bump and the probe bump to provide a first reflow, wherein after the first reflow, the height of a top surface of the probe bump exceeds the height of a top surface of the contact bump.

Collapsible probe tower device and method of forming thereof

A method forms a connecting pillar to a bonding pad of an integrated circuit. A seed layer is formed over the bond pad. Photoresist is deposited over the integrated circuit. An opening is formed in the photoresist over the bond pad. The connecting pillar is formed in the opening by plating.

Semiconductor devices with compliant interconnects

A method for bonding a wire to a substrate includes forming a wire ball at a working tip of a capillary and contacting the wire ball to a substrate via the capillary. The method also includes driving a protrusion at the working tip of the capillary into contact with a region of the substrate surrounding the wire ball. A capillary for wire bonding includes a working face, an annular chamfer section, and a cylindrical bore offsetting the annular chamfer section from the working face. A capillary for wire bonding includes a capillary body comprising a working tip having a working face. The capillary body defines an axial passage extending from the working face along a longitudinal axis of the capillary. The axial passage includes a cylindrical bore extending internally from the working face, and a first annular chamfer having a major diameter defined by the cylindrical bore.

Wire bonding capillary with working tip protrusion

An integrated circuit package includes a substrate having a heat conducting portion integrally formed with a heat dissipating portion. First and second integrated circuit dies are mounted to opposite sides of the heat conducting portion of the substrate. The first and second integrated circuit dies may each be packaged as flip-chip configurations. Electrical connections between contact pads on the first and second integrated circuit dies may be formed through openings formed in the heat conducting portion of the substrate. The heat dissipating portion may be positioned externally from a location between the first and second integrated circuit dies so that it dissipates heat away from the integrated circuit package into the surrounding environment.

Growing community of inventors

New Braunfels, TX, United States of America

Trent Uehling