Qualcomm Incorporated

Singulos Research Inc.

Trent McClements

Bradley Quinton

Andrew Hughes

Sanjiv Taneja

Scott Chin

Michael Scott Lee

Bozena Kaminska

Sheida Alan

In an aspect, the present disclosure provides a method of generating scale selective training data for use in training a machine learning system to support scale selective image classification tasks, comprising obtaining a plurality of images comprising an object of interest at a plurality of image scales; assigning a desired label to each of the plurality of images based on an image scale of the object of interest in the each image, wherein the desired label comprises an in-scope response when the image scale comprises an in-scope image scale, and generating a set of training data for use in training the machine learning system to predict a scale of the object of interest, the training data comprising the plurality of images and corresponding desired labels.

Scale selective machine learning system and method

In an aspect, the present disclosure provides a method of providing a dimensionally aware prediction for an object in an image captured by an image sensor, using a scale selective machine learning system, comprising: obtaining an input comprising image data of an object at an input image scale; generating a plurality of variant images based on re-scaling the input with a plurality of different image scaling factors, each variant image comprising the object at a variant image scale; generating a plurality of scale selective predictions based on the plurality of variant images, and assigning an in-scope response when the variant image comprises the object at an in-scope image scale, and determining a location prediction for the object based on a scale selective prediction comprising the in-scope response.

Dimensionally aware machine learning system and method

Processing image data using deep neural networks is critical to many systems that desire to understand objects and their environment using camera sensors. Image scaling is a fundamental processing task required when managing image data. Although it is possible to scale image data using standard computer or graphics processors it would be highly advantageous in terms of throughput, latency and power consumption to manage image scaling using dedicated neural network hardware. The inventions contained herein provides methods to use existing neural network hardware to preform image scaling functions. Further, the inventions contained herein describe additional circuitry that can be added to neural network hardware to further enhance image scaling capabilities and efficiencies.

Method and apparatus for efficient non-integer scaling in neural network accelerators

The present disclosures provides systems and methods for generating composite based data for use in machine learning systems, such as for use in training a machine learning system on the composite based data to identify an object of interest. In an aspect, a method of generating composite based data for use in training machine learning systems comprises: receiving a plurality of images, each of the plurality of images having a corresponding label; generating a composite image comprising the plurality of images, each of the plurality of images occupying a region of the composite image; generating a response map for the composite image, the response map having a plurality of response entries, each response entry encoded with a desired label corresponding to a fragment of the composite image, and generating composite data comprising the desired label of a response entry and image data corresponding to the fragment of the composite image.

System and method for composite training in machine learning architectures

The present disclosure provides an apparatus and method for training a machine learning engine configured to determine whether an object in a two dimensional (2D) image is in-scope or out-of-scope relative to the one or more 3D objects that includes receiving a 3D model of each of the one or more 3D objects, for each 3D model receiving a set of specifications and thresholds for the 3D model, augmenting the specifications of the 3D model to generate a plurality of augmented 3D models, and generating auxiliary training data based on the plurality of augmented 3D models, and utilizing the auxiliary training data to train the machine learning engine. The present disclosure also provides an apparatus and method for training a machine learning engine that includes receiving sampling parameters related to a system of interest, sampling a generative model of a generative adversarial network (GAN) based on the sampling parameters to generate auxiliary input data, inputting the auxiliary input data into a discriminator model of the GAN to generate an auxiliary label associated with each of the auxiliary input data element, and utilizing the auxiliary input data and auxiliary labels as auxiliary training data to train the machine learning engine.

Apparatus and method for generating training data for a machine learning system

A critical-path timing sensor detects set-up timing failures from a functional critical path to a path flip-flop. The functional critical path carries test data during test mode, and normal data during normal device operation. The path flip-flop's D input and Q output are compared by an exclusive-OR (XOR) gate and sampled by an early capture flip-flop that is clocked by a delayed clock, sampling D and Q just after the path flip-flop is clocked. When set-up time fails, D and Q differ just after the clock edge and a timing failure is latched. Timing failures activate a controller to increase VDD, while VDD is reduced in the absence of timing failures. Process variations are accounted for, allowing for lower power or faster operation. A margin delay between the functional critical path end and the early capture flip-flop detects timing failures before they occur in the path flip-flop.

Circuitry and method for critical path timing speculation to enable process variation compensation via voltage scaling

Toggling functional critical path timing sensors measure delays in toggling functional critical paths that continuously receive patterns from an aging pattern generator. Wear is accelerated. A margin delay adjustment controller sweeps margin delays until failures occur to measure delays. The margin delay is then adjusted in functional critical path timing sensors that add the margin delay to functional critical paths that carry user data or chip controls during normal operation. When the path delays fail to meet requirements, the functional critical path timing sensors signal a controller to increase VDD. When no failures occur over a period of time, the controller decreases VDD. Wear on the toggling functional critical paths is accelerated using both toggle and low-transition-density patterns. Circuit aging is compensated for by increasing margin delays to timing sensors.

Circuitry and method for measuring negative bias temperature instability (NBTI) and hot carrier injection (HCI) aging effects using edge sensitive sampling

Toggling functional critical path timing sensors measure delays in toggling functional critical paths that are replicas of actual critical paths or representations of worst-case delay paths. A Toggle flip-flop or Linear-Feedback-Shift Register (LFSR) drives high-transition-density test patterns to the toggling functional critical paths. When a toggling functional critical path's delay fails to meet set-up timing requirement to a next register, the toggling functional critical path timing sensors signal a controller to increase VDD. When no failures occur over a period of time, the controller decreases VDD. A margin delay buffer adds a delay to the toggling functional critical path before being clocked into an early capture flip-flop. A reference register receives the test pattern without the delay of the toggling functional critical path, and an exclusive-OR (XOR) gate compares outputs of reference and early capture flip-flops to generate timing failure signals to the controller.

Circuitry and method for timing speculation via toggling functional critical paths

User data or constantly toggling functional critical path timing sensors measure delays in actual critical paths that include a RAM. Variable resistors or variable capacitors are added to RAM bit lines for redundant cells to delay bit-line sensing by sense amplifiers. The sense amplifiers' delayed data is compared to non-delayed data from normal selected RAM cells to detect timing failures. Variable resistors or capacitors may also be added between the write drivers and bit lines to delay writing data into the redundant cells. A margin delay adjustment controller sweeps margin delays for constantly toggling paths until failures. A margin delay is then adjusted and added to functional critical paths that carry user data. Functional critical path timing sensors test setup time with the added margin delay. Timing failures cause VDD to increase, while a controller reduces VDD when no failures occur. Actual delays through the RAM adjust VDD.

Circuitry and method for critical path timing speculation in RAMs

CAD software examines delays of paths in a design from design engineers and first selects the longest paths. Then all paths that converge with these longest paths are examined for delays, and a fastest converging path is selected for each of the longest paths. The longest paths are again sorted by the fastest converging delay, and paths with slower converging paths are selected to be Functional Critical Paths (FCP's). Functional critical path timing sensors are added to each FCP to test setup time with an added margin delay. When the margined path delays fail to meet setup requirements, the functional critical path timing sensors signal a controller to increase VDD. When no failures occur over a period of time, the controller decreases VDD. The CAD software can replicate some of the FCP's and add toggle pattern generators and timing sensors and a margin controller to adjust the margin delay.

Method and algorithm for functional critical paths selection and critical path sensors and controller insertion

Described herein are apparatuses and methods for enhancing timing delay fault coverage during testing of functional circuitry. In one embodiment, an apparatus includes functional circuitry for performing functional operations and test logic coupled to the functional circuitry to enhance timing delay fault coverage for the functional circuitry with at-speed test sequences. The test logic includes a plurality of partitions of scan flip-flops and an independent partition scan enable input signal for each partition for enabling or disabling each partition.

Methods and apparatuses to enhance timing delay fault coverage with test logic that includes partitions and scan flip-flops

Described herein are apparatuses and methods for enhancing timing delay fault coverage during testing of functional circuitry. The present design includes a novel at-speed (e.g., at clock speed of functional circuitry during functional mode) mechanism to improve transition delay fault testing. In one embodiment, an apparatus includes functional circuitry for performing functional operations and test logic coupled to the functional circuitry. The test logic enhances timing delay fault coverage for the functional circuitry. The test logic includes scan flip-flops arranged in at least one scan chain and at least one input signal that is generated based on at least one scan override signal for overriding at least one scan enable signal.

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Burnaby, Canada

Trent McClements