Advanced Micro Devices Corporation

Travis Wheatley

Michael T Wisor

James A Treadway

Dan S Mudgett

Wei-Lien Hsu

Christopher Gray

An efficient finite length POW10 calculation for MPEG audio encoding. A method for encoding an audio input signal includes storing a plurality of predetermined tonal values corresponding to a plurality of predetermined power levels. The method also includes receiving a plurality of input values each representative of a power level of a spectral component of the audio input signal at a corresponding frequency sub-band and accessing at least one corresponding tonal value of the plurality of predetermined tonal values. The method further includes generating an encoded output signal representative of the audio input signal by using at least one corresponding tonal value for each of the plurality of input values. Further, the storing of the plurality of predetermined tonal values is performed prior to the receiving of the plurality of input values.

Efficient finite length POW10 calculation for MPEG audio encoding

A method and apparatus for concurrent testing of a plurality of microprocessors, each of which may have a different revision, by creating an abstract base class which specifies the names of a plurality of tests, creating a derived class for each revision and defining each of the tests appropriately for each of the derived classes, instantiating an object from one of the derived classes for each of the microprocessors and executing the tests by reference to the objects. A computer system is configured to be coupled to the microprocessors and, upon execution of a debug/test application on the computer system, the revision of each microprocessor is determined and an object is instantiated from the derived class corresponding to the revision. Each object is thereby dynamically bound to the tests defined for the derived class corresponding to the revision, and references to the tests via the objects automatically execute the test code specific to appropriate revision of the microprocessor.

Method for utilizing virtual hardware descriptions to allow for multi-processor debugging in environments using varying processor revision levels

A method and apparatus for testing one of a plurality of revisions of a microprocessor by creating an abstract base class which specifies the names of a plurality of tests or attributes, creating a derived class for each revision and defining each of the tests or attributes appropriately for each of the derived classes, instantiating an object from one of the derived classes and executing the tests by reference to the object. A computer system is configured to be coupled to a microprocessor which may be any one of a plurality of revisions. Upon execution of a debug/test application on the computer system, the revision of the microprocessor is determined and the object is instantiated from the derived class corresponding to the revision. The object is thereby dynamically bound to the tests defined for the derived class corresponding to the revision and references to each test via the object automatically execute the test code specific to the revision of the microprocessor. The microprocessor may be replaced with a second microprocessor having a second revision. A second object is instantiated from the derived class corresponding to the second revision and the tests are executed via reference to the second object, thereby automatically executing the test code specific to the second revision.

Method to dynamically change microprocessor test software to reflect different silicon revision levels

A method and system for verifying the accuracy of trace data generated by execution of a program on a computer under test, one embodiment of the method comprising scanning the trace data to locate bitmap data corresponding to series of consecutive conditional branches and comparing the number of bits representative of these branches to the number of consecutive conditional branches in the instruction sequence. The trace data includes address entries and bitmap entries. The trace data is scanned in reverse chronological order beginning with the most recent entry to locate an address entry preceding one or more bitmaps which represent a most recent series of conditional branches. Beginning with the instruction at the address contained in the address entry, the program instructions are scanned in program order until a conditional branch is encountered. The branch is counted and the trace data is examined to determine whether the branch was taken and scanning is resumed. The scanning and counting of the conditional branches continues until an instruction which generates a non-bitmap entry is encountered. The number of conditional branches is then compared to the number of bits representative of branches to verify that they are equal. In some embodiments, the target addresses of the branch instructions are also checked to verify that they correspond to the target addresses of the corresponding BTHB entries. Preceding bitmap entries are each checked in this manner until all of the trace data has been verified.

Method for verifying branch trace history buffer information

A method and system for determining the sequence of execution of instructions in a computer under test using trace data generated upon execution of certain ones of the instructions. In one embodiment, the method comprises locating an initial entry in the trace data and scanning the instructions in program order beginning with an instruction indicated by the initial entry. When a branch instruction is encountered, the trace data is examined to determine the subsequently executed instruction. If the branch is unconditional, a corresponding address entry in the trace data indicates the address of the next instruction. If the branch is conditional, a corresponding bitmap entry in the trace data contains a bit which indicates whether the branch was taken. From this bit and the instructions themselves, the next instruction is determined. The bitmap entry contains a series of bits, each of which can indicate whether a conditional branch was taken, so that a single bitmap entry can represent a series of conditional branches.

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Austin, TX, United States of America

Travis Wheatley