Intel Corporation

Daedalus Prime LLC

Travis T Schluessler

Joydeep Ray

Abhishek R Appu

Altug Koker

Prasoonkumar Surti

John H Feit

Nikos Kaburlasos

Jacek Kwiatkowski

Balaji Vembu

Ankur N Shah

Devan Burke

Jonathan Kennedy

Subramaniam M Maiyuran

Kamal Sinha

Michael Apodaca

Abhishek Venkatesh

Karthik Vaidyanathan

Linda L Hurd

Jeffery S Boles

Wenyin Fu

Atsuo Kuwahara

Kiran Chand Veernapu

Elmoustapha Ould-Ahmed-Vall

Adam T Lake

Gabor Liktor

Josh B Mastronarde

Kai Xiao

John G Gierach

David M Durham

Tomer Bar-On

Murali Ramadoss

Philip R Laws

Feng Chen

Eriko Nurvitadhi

Ben J Ashbaugh

Louis Feng

Eric J Hoekstra

Ravi L Sahita

Vasanth Ranganathan

Guei-Yuan Lueh

Justin E Gottschlich

Sara S Baghsorkhi

Nadathur Rajagopalan Satish

Farshad Akhbari

Narayan Srinivasa

Nicolas C Galoppo Von Borries

David M Puffer

Rajkishore Barik

Peter L Doyle

Dukhwan Kim

Tsung-Han Lin

Bhushan M Borole

Sanjeev S Jahagirdar

Hugues Labbe

Tomasz Janczak

Saurabh Sharma

Hormuzd M Khosravi

James M Holland

Narayan Biswal

Stanley J Baran

Gokcen Cilingir

Nilesh V Shah

Barnan Das

Andrew T Lauritzen

Archie Sharma

Mayuresh M Varerkar

Carsten Benthin

Aravindh V Anantaraman

Russell Jerome Fenger

Vincent J Zimmer

Uday R Savagaonkar

Deepak Shashidhar Vembar

Supratim Pal

Sameer Kp

David M Cimini

Aditya Navale

Chandrasekaran Sakthivel

Pattabhiraman K

Thomas F Raoux

Mazhar I Memon

Kapil Sood

Ryan Donovan Wells

Ingo Wald

James A Valerio

Yuheng Zhang

Hema Chand Nalluri

Erik J Johnson

Peng Guo

Carlos V Rozas

Anbang Yao

John Charles Weast

Jon N Hasselgren

Karanvir S Grewal

Xiaoming Chen

Selvakumar Panneer

Amit Bleiweiss

Liwei Ma

Chandra S Gurram

Vikranth Vemulapalli

Zhe Wang

Described herein are various embodiments of reducing dynamic power consumption within a processor device. One embodiment provides a technique for dynamic link width adjustment based on throughput demand for client of an interconnect fabric. One embodiment provides for a parallel processor comprising an interconnect fabric including a dynamically configurable bus widths and frequencies.

Interconnect fabric link width reduction to reduce instantaneous power consumption

A graphics processing apparatus includes a graphics processor and a constant cache. The graphics processor has a number of execution instances that will generate requests for constant data from the constant cache. The constant cache stores constants of multiple constant types. The constant cache has a single level of hierarchy to store the constant data. The constant cache has a banking structure based on the number of execution instances, where the execution instances generate requests for the constant data with unified messaging that is the same for the different types of constant data.

High performance constant cache and constant access mechanisms

Apparatus and method for acceleration data structure refit. For example, one embodiment of an apparatus comprises: a ray generator to generate a plurality of rays in a first graphics scene; a hierarchical acceleration data structure generator to construct an acceleration data structure comprising a plurality of hierarchically arranged nodes including inner nodes and leaf nodes stored in a memory in a depth-first search (DFS) order; traversal hardware logic to traverse one or more of the rays through the acceleration data structure; intersection hardware logic to determine intersections between the one or more rays and one or more primitives within the hierarchical acceleration data structure; a node refit unit comprising circuitry and/or logic to read consecutively through at least the inner nodes in the memory in reverse DFS order to perform a bottom-up refit operation on the hierarchical acceleration data structure.

Apparatus and method for acceleration data structure refit

An embodiment of an electronic processing system may include an application processor, persistent storage media communicatively coupled to the application processor, a graphics subsystem communicatively coupled to the application processor, a sense engine communicatively coupled to the graphics subsystem to provide sensed information, a focus engine communicatively coupled to the sense engine and the graphics subsystem to provide focus information, a motion engine communicatively coupled to the sense engine, the focus engine, and the graphics subsystem to provide motion information, and a motion biased foveated renderer communicatively coupled to the motion engine, the focus engine, the sense engine to adjust one or more parameters of the graphics subsystem based on one or more of the sense information, the focus information, and the motion information. Other embodiments are disclosed and claimed.

Motion biased foveated renderer

Embodiments provide mechanisms to facilitate compute operations for deep neural networks. One embodiment comprises a graphics processing unit comprising one or more multiprocessors, at least one of the one or more multiprocessors including a register file to store a plurality of different types of operands and a plurality of processing cores. The plurality of processing cores includes a first set of processing cores of a first type and a second set of processing cores of a second type. The first set of processing cores are associated with a first memory channel and the second set of processing cores are associated with a second memory channel.

Compute optimization mechanism for deep neural networks

An apparatus comprising a sorting unit to sort primitives of a graphics image, the primitives to be grouped, each group to form a first level node of a hierarchical acceleration structure; a parallel reconfigurable clustering array to construct the hierarchical acceleration structure, the parallel reconfigurable clustering array comprising a plurality of processing clusters, each cluster comprising: parallel efficiency analysis circuitry to evaluate different groupings of the first level nodes for a next level of the hierarchical acceleration structure to determine efficiency values for the different groupings; and node merge circuitry to merge the first level nodes based on the efficiency values to form second level nodes.

Unified architecture for BVH construction based on hardware pre-sorting and a parallel, reconfigurable clustering array

Methods and apparatus relating to techniques for avoiding cache lookup for cold cache. In an example, an apparatus comprises logic, at least partially comprising hardware logic, to collect user information for a user of a data processing device, generate a user profile for the user of the data processing device from the user information, and set a power profile a processor in the data processing device using the user profile. Other embodiments are also disclosed and claimed.

Processor power management

Apparatus and method for speculative execution of hit and intersection shaders on programmable ray tracing architectures. For example, one embodiment of an apparatus comprises: single-instruction multiple-data (SIMD) or single-instruction multiple-thread (SIMT) execution units (EUs) to execute shaders; and ray tracing circuitry to execute a ray traversal thread, the ray tracing engine comprising: traversal/intersection circuitry, responsive to the traversal thread, to traverse a ray through an acceleration data structure comprising a plurality of hierarchically arranged nodes and to intersect the ray with a primitive contained within at least one of the nodes; and shader deferral circuitry to defer and aggregate multiple shader invocations resulting from the traversal thread until a particular triggering event is detected, wherein the multiple shaders are to be dispatched on the EUs in a single shader batch upon detection of the triggering event.

Speculative execution of hit and intersection shaders on programmable ray tracing architectures

An apparatus, method and system is described herein for efficiently balancing performance and power between processing elements based on measured workloads. If a workload of a processing element indicates that it is a bottleneck, then its performance may be increased. However, if a platform or integrated circuit including the processing element is already operating at a power or thermal limit, the increase in performance is counterbalanced by a reduction or cap in another processing elements performance to maintain compliance with the power or thermal limit. As a result, bottlenecks are identified and alleviated by balancing power allocation, even when multiple processing elements are operating at a power or thermal limit.

Method, apparatus, and system for energy efficiency and energy conservation including power and performance balancing between multiple processing elements and/or a communication bus

Systems, apparatuses and methods may provide away to render augmented reality (AR) and/or virtual reality (VR) sensory enhancements using ray tracing. More particularly, systems, apparatuses and methods may provide a way to normalize environment information captured by multiple capture devices, and calculate, for an observer, the sound sources or sensed events vector paths. The systems, apparatuses and methods may detect and/or manage one or more capture devices and assign one or more the capture devices based on one or more conditions to provide observer an immersive VR/AR experience.

Augmented reality virtual reality ray tracing sensory enhancement system, apparatus and method

An apparatus to facilitate compute optimization is disclosed. The apparatus includes a at least one processor to perform operations to implement a neural network and compute logic to accelerate neural network computations.

In accordance with some embodiments, the render rate is varied across and/or up and down the display screen. This may be done based on where the user is looking in order to reduce power consumption and/or increase performance. Specifically the screen display is separated into regions, such as quadrants. Each of these regions is rendered at a rate determined by at least one of what the user is currently looking at, what the user has looked at in the past and/or what it is predicted that the user will look at next. Areas of less focus may be rendered at a lower rate, reducing power consumption in some embodiments.

Regional adjustment of render rate

Methods, systems and apparatuses may provide for technology that determines measured timing data in response to a presentation request from an application, wherein the measured timing data is associated with one or more previous frames and the presentation request is associated with one or more subsequent frames. The technology may also determine scheduling times for the subsequent frame(s) based on the measured timing data, wherein the scheduling times include a simulation time, a rendering time, a driver submission time, a hardware submission time, and a display time. In one example, the technology controls a pacing of the subsequent frame(s) on a display in accordance with the scheduling times.

Frame pacing for improved experiences in 3D applications

A system and method for high performance secure access to a trusted platform module on a hardware virtualization platform. Example instructions partition resources of the host system to allocate (a) first resources of the host system for a first virtual machine and (b) second resources of the host system for a second virtual machine, wherein the resources of the host system include memory resources and a trusted platform module, the first virtual machine to run a first guest operating system and the second virtual machine to run a second guest operating system, wherein the first guest operating system is to run in a first isolated environment, the second guest operating system is to run in a second isolated environment; implement a virtual trusted platform module to support encryption for the first virtual machine; and protect the first resources and the second resources from unauthorized access.

System and method for high performance secure access to a trusted platform module on a hardware virtualization platform

Growing community of inventors

Hillsboro, OR, United States of America

Travis T Schluessler