International Business Machines Corporation

Advanced Micro Devices Corporation

Travis S Merrill

David G Brochu, Jr

Timothy Dooling Sullivan

Tom C Lee

Fen Chen

Alvin Wayne Strong

Steven W Mittl

Deborah M Massey

Roger Aime Dufresne

Oliver Aubel

Michael Anthony Shinosky

Dimitris P Ioannou

Stanley W Polchlopek

Test structures for simultaneously testing for electromigration or stress migration fails and time dependent dielectric breakdown fails in integrated circuits, test circuits using four test structures arranged as a bridge balance circuit and methods of testing using the test circuits. The electromigration or stress migration portions of the test structures include via chains of wire segments connected in series by electrically conductive vias, the wire segments formed in at least two adjacent wiring levels of an integrated circuit. The time dependent dielectric breakdown portions of the test structures include digitized wire structures in one of the at least two adjacent wiring levels adjacent to a less than whole portion of the wire segments in the same wiring level as the digitized wire structures.

Test structure, method and circuit for simultaneously testing time dependent dielectric breakdown and electromigration or stress migration

A method establishes an initial voltage in a ring oscillator and a logic circuit of an integrated circuit device. Following this, the method enables the operating state of the ring oscillator. After enabling the operating state of the ring oscillator, the method steps up to a stressing voltage in the ring oscillator. The initial voltage is approximately one-half the stressing voltage. The stressing voltage creates operating-level stress within the ring oscillator. The method measures the operating-level frequency within the ring oscillator using an oscilloscope (after stepping up to the stressing voltage).

Measuring bias temperature instability induced ring oscillator frequency degradation

Methods, systems and program products are disclosed for performing a stress test of a line in an integrated circuit (IC) chip. One embodiment of the method includes: applying a constant current Ito the line; and stress testing the line while applying the constant current Isuch that the constant current Iis not altered by a resistance change due to an onset of electromigration.

IC chip stress testing

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Rutland, VT, United States of America

Travis S Merrill